{"id":"https://openalex.org/W1989069093","doi":"https://doi.org/10.1145/1973009.1973074","title":"Circuit design of a dual-versioning L1 data cache for optimistic concurrency","display_name":"Circuit design of a dual-versioning L1 data cache for optimistic concurrency","publication_year":2011,"publication_date":"2011-05-02","ids":{"openalex":"https://openalex.org/W1989069093","doi":"https://doi.org/10.1145/1973009.1973074","mag":"1989069093"},"language":"en","primary_location":{"id":"doi:10.1145/1973009.1973074","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/2117/110488","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062904766","display_name":"Azam Seyedi","orcid":"https://orcid.org/0000-0002-2708-9522"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Azam Seyedi","raw_affiliation_strings":["BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049697257","display_name":"Adri\u00e0 Armejach","orcid":"https://orcid.org/0000-0003-2869-668X"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Adri\u00e0 Armejach","raw_affiliation_strings":["BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084390427","display_name":"Adri\u00e1n Cristal","orcid":"https://orcid.org/0000-0003-1277-9296"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]},{"id":"https://openalex.org/I4210131846","display_name":"Artificial Intelligence Research Institute","ror":"https://ror.org/03c0ach84","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210131846"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Adri\u00e1n Cristal","raw_affiliation_strings":["BSC - Microsoft Research Centre & IIIA - Artificial Intelligence Research Institute CSIC, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"BSC - Microsoft Research Centre & IIIA - Artificial Intelligence Research Institute CSIC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848","https://openalex.org/I4210131846"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075162875","display_name":"Osman \u00dcnsal","orcid":"https://orcid.org/0000-0002-0544-9697"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Osman S. Unsal","raw_affiliation_strings":["BSC - Microsoft Research Centre, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"BSC - Microsoft Research Centre, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047397553","display_name":"Ibrahim Hur","orcid":"https://orcid.org/0009-0003-8375-3963"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ibrahim Hur","raw_affiliation_strings":["BSC - Microsoft Research Centre, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"BSC - Microsoft Research Centre, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020844763","display_name":"Mateo Valero","orcid":"https://orcid.org/0000-0003-2917-2482"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Mateo Valero","raw_affiliation_strings":["BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5062904766"],"corresponding_institution_ids":["https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":1.7974,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.85343399,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"325","last_page":"330"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8216112852096558},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7406851649284363},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.7243387699127197},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.5276834964752197},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.5234795808792114},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5014150142669678},{"id":"https://openalex.org/keywords/software-versioning","display_name":"Software versioning","score":0.4992218017578125},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4931282699108124},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.416444331407547},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41568851470947266},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.39972996711730957},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39426928758621216},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3560621738433838},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3487705588340759}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8216112852096558},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7406851649284363},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.7243387699127197},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.5276834964752197},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.5234795808792114},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5014150142669678},{"id":"https://openalex.org/C198140048","wikidata":"https://www.wikidata.org/wiki/Q10859422","display_name":"Software versioning","level":3,"score":0.4992218017578125},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4931282699108124},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.416444331407547},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41568851470947266},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.39972996711730957},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39426928758621216},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3560621738433838},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3487705588340759},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1973009.1973074","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:dnet:upcommonspor::6c106ee53ce7348b35b582ff04324e6f","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/110488","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":{"id":"pmh:oai:dnet:upcommonspor::6c106ee53ce7348b35b582ff04324e6f","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/110488","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320308943","display_name":"Microsoft Research","ror":"https://ror.org/00d0nc645"},{"id":"https://openalex.org/F4320317579","display_name":"HiPEAC Network","ror":null},{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320323868","display_name":"Barcelona Supercomputing Center","ror":"https://ror.org/05sd8tv96"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1608508249","https://openalex.org/W1949737515","https://openalex.org/W2021030008","https://openalex.org/W2029479717","https://openalex.org/W2062774241","https://openalex.org/W2085809676","https://openalex.org/W2099661831","https://openalex.org/W2108449262","https://openalex.org/W2110160974","https://openalex.org/W2110710544","https://openalex.org/W2157024459","https://openalex.org/W2158609250","https://openalex.org/W2163654949","https://openalex.org/W2166411696","https://openalex.org/W3021887419","https://openalex.org/W3103339143","https://openalex.org/W4285719527","https://openalex.org/W4298077439"],"related_works":["https://openalex.org/W2184371594","https://openalex.org/W4312759433","https://openalex.org/W2148571123","https://openalex.org/W2801630946","https://openalex.org/W273173017","https://openalex.org/W1652973653","https://openalex.org/W2135365633","https://openalex.org/W1988497841","https://openalex.org/W2152423944","https://openalex.org/W1988485265"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,34,38,76],"novel":[4],"L1":[5,79],"data":[6,80],"cache":[7,26,81],"design":[8,73],"with":[9,82,152],"dual-versioning":[10,78,135],"SRAM":[11],"cells":[12,64],"(dvSRAM)":[13],"for":[14],"chip":[15],"multi-processors":[16],"(CMP)":[17],"that":[18,106,114,146],"implement":[19],"optimistic":[20,110],"concurrency":[21,111],"proposals.":[22],"In":[23],"this":[24],"new":[25],"architecture,":[27],"each":[28],"dvSRAM":[29],"cell":[30,36,136],"has":[31],"two":[32,43],"cells,":[33],"main":[35,61],"and":[37,57,62,74,90,113,140],"secondary":[39,63],"cell,":[40],"which":[41,94],"keep":[42],"versions":[44],"of":[45,69,109,125,133],"the":[46,60,66,70,126,131,134],"same":[47],"data.":[48],"These":[49],"values":[50],"can":[51,115,149],"be":[52,150],"accessed,":[53],"modified,":[54],"moved":[55],"back":[56],"forth":[58],"between":[59],"within":[65],"access":[67],"time":[68],"cache.":[71],"We":[72,99],"simulate":[75],"32-KB":[77],"45-nm":[83],"CMOS":[84],"technology":[85],"at":[86],"2GHz":[87],"processor":[88],"frequency":[89],"1V":[91],"supply":[92],"voltage,":[93],"we":[95,122],"describe":[96],"in":[97,137],"detail.":[98],"also":[100],"introduce":[101],"three":[102],"well-known":[103],"use":[104,108,127],"cases":[105,128],"make":[107],"execution":[112],"benefit":[116],"from":[117],"our":[118],"proposed":[119],"design.":[120],"Moreover,":[121],"evaluate":[123],"one":[124],"to":[129],"show":[130,145],"impact":[132],"both":[138],"performance":[139],"energy":[141,155],"consumption.":[142],"Our":[143],"experiments":[144],"large":[147],"speedups":[148],"achieved":[151],"acceptable":[153],"overall":[154],"dissipation.":[156]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}