{"id":"https://openalex.org/W2040082102","doi":"https://doi.org/10.1145/1973009.1973054","title":"Simulation-based equivalence checking between SystemC models at different levels of abstraction","display_name":"Simulation-based equivalence checking between SystemC models at different levels of abstraction","publication_year":2011,"publication_date":"2011-05-02","ids":{"openalex":"https://openalex.org/W2040082102","doi":"https://doi.org/10.1145/1973009.1973054","mag":"2040082102"},"language":"en","primary_location":{"id":"doi:10.1145/1973009.1973054","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086566894","display_name":"Daniel Gro\u00dfe","orcid":"https://orcid.org/0000-0002-1490-6175"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Daniel Gro\u00dfe","raw_affiliation_strings":["University of Bremen, Bremen, Germany","[University of Bremen, Bremen, Germany]"],"affiliations":[{"raw_affiliation_string":"University of Bremen, Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]},{"raw_affiliation_string":"[University of Bremen, Bremen, Germany]","institution_ids":["https://openalex.org/I180437899"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011857356","display_name":"Markus Gro\u00df","orcid":null},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Markus Gro\u00df","raw_affiliation_strings":["University of Bremen, Bremen, Germany","[University of Bremen, Bremen, Germany]"],"affiliations":[{"raw_affiliation_string":"University of Bremen, Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]},{"raw_affiliation_string":"[University of Bremen, Bremen, Germany]","institution_ids":["https://openalex.org/I180437899"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075576417","display_name":"Ulrich K\u00fchne","orcid":"https://orcid.org/0000-0002-0855-8223"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ulrich K\u00fchne","raw_affiliation_strings":["LSV ENS de Cachan, Cachan, France"],"affiliations":[{"raw_affiliation_string":"LSV ENS de Cachan, Cachan, France","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071742136","display_name":"Rolf Drechsler","orcid":"https://orcid.org/0000-0002-9872-1740"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Drechsler","raw_affiliation_strings":["University of Bremen, Bremen, Germany","[University of Bremen, Bremen, Germany]"],"affiliations":[{"raw_affiliation_string":"University of Bremen, Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]},{"raw_affiliation_string":"[University of Bremen, Bremen, Germany]","institution_ids":["https://openalex.org/I180437899"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5086566894"],"corresponding_institution_ids":["https://openalex.org/I180437899"],"apc_list":null,"apc_paid":null,"fwci":0.7556,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.723585,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"223","last_page":"228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8994901180267334},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8498777747154236},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.8027068376541138},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.6156228184700012},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.5954626798629761},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.5765647888183594},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.5640091300010681},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5495783090591431},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.49094656109809875},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4779410660266876},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.47682327032089233},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3522781729698181},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3498532772064209},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33500999212265015}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8994901180267334},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8498777747154236},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.8027068376541138},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.6156228184700012},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.5954626798629761},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.5765647888183594},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.5640091300010681},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5495783090591431},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.49094656109809875},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4779410660266876},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.47682327032089233},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3522781729698181},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3498532772064209},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33500999212265015},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1973009.1973054","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1536710422","https://openalex.org/W1555791645","https://openalex.org/W1607765501","https://openalex.org/W1967501629","https://openalex.org/W2006397252","https://openalex.org/W2105389779","https://openalex.org/W2130051797","https://openalex.org/W2139171217","https://openalex.org/W2142916228","https://openalex.org/W2144495128","https://openalex.org/W2148740615","https://openalex.org/W2151174323","https://openalex.org/W2167718692","https://openalex.org/W2169782229","https://openalex.org/W2170821802","https://openalex.org/W2171078653","https://openalex.org/W2171999426","https://openalex.org/W2467331656","https://openalex.org/W4253669045","https://openalex.org/W6719751381","https://openalex.org/W7000400498"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2532163536","https://openalex.org/W2266880325","https://openalex.org/W2069603759","https://openalex.org/W2533881872","https://openalex.org/W3146089259","https://openalex.org/W2112120387","https://openalex.org/W1981924702","https://openalex.org/W2612875731","https://openalex.org/W2204090679"],"abstract_inverted_index":{"Today":[0],"for":[1,30,183],"System-on-Chips":[2],"(SoCs)":[3],"companies":[4],"Electronic":[5],"System":[6],"Level(ESL)":[7],"design":[8],"is":[9,49,60,102,119,170,185],"the":[10,27,50,57,64,75,80,108,125,155,176,180,188,191,197,206],"established":[11],"approach.":[12],"Abstraction":[13],"and":[14],"standardized":[15],"communication":[16],"interfaces":[17],"based":[18,120],"on":[19,121],"SystemC":[20,152],"Transaction":[21],"Level":[22],"Modeling":[23],"(TLM)":[24],"have":[25,70],"become":[26],"core":[28],"component":[29],"ESL":[31,37,117],"design.":[32],"The":[33,67],"abstract":[34],"models":[35,87,157],"in":[36,112,116,139,150],"flows":[38,118],"are":[39,158,203],"stepwise":[40],"refined":[41],"down":[42],"to":[43,71,74,78,96,107,145,205],"hardware.":[44],"In":[45,164,178],"this":[46,101,140],"context":[47],"verification":[48,127],"major":[51],"bottleneck:":[52],"After":[53],"each":[54],"refinement":[55],"step":[56],"resulting":[58],"model":[59],"simulated":[61],"again":[62],"with":[63,166],"same":[65],"testbench.":[66],"simulation":[68],"results":[69,77],"be":[72],"compared":[73],"previous":[76],"check":[79],"functional":[81],"equivalence":[82,114,136],"of":[83,91],"both":[84],"models.":[85,153],"For":[86],"at":[88],"lower":[89],"levels":[90],"abstraction":[92],"strong":[93],"approaches":[94],"exist":[95],"formally":[97],"prove":[98],"equivalence.":[99],"However,":[100],"not":[103,201],"possible":[104],"here":[105],"due":[106],"TLM":[109],"abstraction.":[110],"Hence,":[111],"practice":[113],"checking":[115,137],"simulation.":[122],"Since":[123],"implementing":[124],"necessary":[126],"environment":[128],"requires":[129],"a":[130,161],"huge":[131],"effort,":[132],"we":[133],"propose":[134],"an":[135],"framework":[138,143,189],"paper.":[141],"Our":[142],"allows":[144],"easily":[146],"compare":[147],"variable":[148,198],"accesses":[149,199],"different":[151],"Therefore,":[154],"two":[156],"co-simulated":[159],"using":[160],"client-server":[162],"architecture.":[163],"combination":[165],"multi-threading":[167],"our":[168],"approach":[169],"very":[171],"efficient":[172],"as":[173],"shown":[174],"by":[175,187],"experiments.":[177],"addition,":[179],"time":[181],"required":[182],"debugging":[184],"reduced":[186],"since":[190],"respective":[192],"source":[193],"code":[194],"references":[195],"where":[196],"did":[200],"match":[202],"presented":[204],"user.":[207]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}