{"id":"https://openalex.org/W2014857766","doi":"https://doi.org/10.1145/1973009.1973049","title":"Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization","display_name":"Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization","publication_year":2011,"publication_date":"2011-05-02","ids":{"openalex":"https://openalex.org/W2014857766","doi":"https://doi.org/10.1145/1973009.1973049","mag":"2014857766"},"language":"en","primary_location":{"id":"doi:10.1145/1973009.1973049","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024121703","display_name":"Feifei Niu","orcid":"https://orcid.org/0000-0002-6322-6934"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Feifei Niu","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101929509","display_name":"Qiang Zhou","orcid":"https://orcid.org/0000-0003-1348-8861"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Zhou","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058812423","display_name":"Hailong Yao","orcid":"https://orcid.org/0000-0002-8750-3086"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hailong Yao","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100894724","display_name":"Yici Cai","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yici Cai","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053303853","display_name":"Jianlei Yang","orcid":"https://orcid.org/0000-0001-8424-7040"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianlei Yang","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111946180","display_name":"C. N. Sze","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. N. Sze","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX, USA","IBM Austin research laboratory, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin research laboratory, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5024121703"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.7949,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.7493391,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"199","last_page":"204"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.8247436285018921},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.670218825340271},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6035184264183044},{"id":"https://openalex.org/keywords/obstacle","display_name":"Obstacle","score":0.5959870219230652},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5828521251678467},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5323904752731323},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.524637758731842},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.49155887961387634},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46987730264663696},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.41747161746025085},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3524649143218994},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34200453758239746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2692680060863495},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18015089631080627},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.13606902956962585},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11328142881393433}],"concepts":[{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.8247436285018921},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.670218825340271},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6035184264183044},{"id":"https://openalex.org/C2776650193","wikidata":"https://www.wikidata.org/wiki/Q264661","display_name":"Obstacle","level":2,"score":0.5959870219230652},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5828521251678467},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5323904752731323},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.524637758731842},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.49155887961387634},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46987730264663696},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.41747161746025085},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3524649143218994},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34200453758239746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2692680060863495},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18015089631080627},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.13606902956962585},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11328142881393433},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1973009.1973049","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1967474595","https://openalex.org/W1968636796","https://openalex.org/W1974094282","https://openalex.org/W2004375829","https://openalex.org/W2025594056","https://openalex.org/W2068121061","https://openalex.org/W2117616504","https://openalex.org/W2123316553","https://openalex.org/W2125164085","https://openalex.org/W2127434816","https://openalex.org/W2127611603","https://openalex.org/W2136768070","https://openalex.org/W2142850552","https://openalex.org/W2158130267","https://openalex.org/W2160252016","https://openalex.org/W2600578627","https://openalex.org/W2952137074"],"related_works":["https://openalex.org/W2116259070","https://openalex.org/W2123512677","https://openalex.org/W4232019485","https://openalex.org/W4327499872","https://openalex.org/W2164834710","https://openalex.org/W2128528443","https://openalex.org/W2028052815","https://openalex.org/W2066822161","https://openalex.org/W1866979339","https://openalex.org/W2771228069"],"abstract_inverted_index":{"Buered":[0],"clock":[1,41,55,88],"tree":[2,56,89],"synthesis":[3],"(CTS)":[4],"is":[5],"increasingly":[6],"critical":[7],"as":[8],"VLSI":[9],"technology":[10],"continually":[11],"scales":[12],"down.":[13],"Many":[14],"researches":[15],"have":[16],"been":[17],"done":[18],"on":[19,63,134],"this":[20],"topic":[21],"due":[22],"to":[23,39,67],"its":[24],"key":[25],"role":[26],"in":[27,139,149,158],"CTS,":[28],"but":[29],"current":[30],"approaches":[31],"either":[32],"lack":[33],"the":[34,69,87,93,116,152],"obstacle-avoiding":[35,50],"functionality":[36],"or":[37],"lead":[38],"large":[40],"latency":[42,127],"and/or":[43],"skew.":[44],"This":[45],"paper":[46],"presents":[47],"a":[48,107],"new":[49],"CTS":[51,84,120],"approach":[52,85,121],"with":[53,92,122],"separate":[54],"construction":[57,90],"and":[58,81,106,126,132,136],"buer":[59,104,110],"insertion":[60,101,111],"stages":[61],"based":[62],"an":[64],"integral":[65],"view":[66],"explore":[68],"global":[70],"optimization":[71,76],"space.":[72],"Aiming":[73],"at":[74],"skew":[75,125,140,150],"under":[77],"constraints":[78],"of":[79,102,118],"slew":[80],"obstacles,":[82],"our":[83,119],"features":[86],"stage":[91],"obstacle-aware":[94],"topology":[95],"generation":[96],"algorithm":[97,156],"called":[98],"OBB,":[99],"balanced":[100,154],"candidate":[103],"positions,":[105],"fast":[108],"heuristic":[109,145],"algorithm.":[112],"Experimental":[113],"results":[114],"show":[115],"eectiveness":[117],"significantly":[123],"improved":[124],"than":[128,141,151],"[6]":[129],"by":[130],"46%":[131],"63%":[133],"average,":[135],"15.3%":[137],"reduction":[138],"[5].":[142],"Our":[143],"OBB":[144],"obtains":[146],"36%":[147],"improvement":[148],"classic":[153],"bipartition":[155],"(BB)":[157],"[10].":[159]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
