{"id":"https://openalex.org/W2019084430","doi":"https://doi.org/10.1145/1973009.1973040","title":"A design methodology for the automatic sizing of standard-cell libraries","display_name":"A design methodology for the automatic sizing of standard-cell libraries","publication_year":2011,"publication_date":"2011-05-02","ids":{"openalex":"https://openalex.org/W2019084430","doi":"https://doi.org/10.1145/1973009.1973040","mag":"2019084430"},"language":"en","primary_location":{"id":"doi:10.1145/1973009.1973040","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973040","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072400487","display_name":"Christian Pilato","orcid":"https://orcid.org/0000-0001-9315-1788"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Christian Pilato","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy","Politecnico di Milano, Milan (Italy)#TAB#"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano, Milan (Italy)#TAB#","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028565685","display_name":"Fabrizio Ferrandi","orcid":"https://orcid.org/0000-0003-0301-4419"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabrizio Ferrandi","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy","Politecnico di Milano, Milan (Italy)#TAB#"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano, Milan (Italy)#TAB#","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065985032","display_name":"Davide Pandini","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Pandini","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza (MI), Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza (MI), Italy","institution_ids":["https://openalex.org/I4210154781"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5072400487"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.08331143,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"151","last_page":"156"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.8548642992973328},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.816727876663208},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.7632684111595154},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7114265561103821},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5819781422615051},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.560697615146637},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5576136112213135},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5446304082870483},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5413034558296204},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5184842944145203},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.495159775018692},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4361163377761841},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42997533082962036},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4286423325538635},{"id":"https://openalex.org/keywords/decimation","display_name":"Decimation","score":0.41328057646751404},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4113900363445282},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4010372757911682},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.33208131790161133},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3261224329471588},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.28224658966064453},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.26354092359542847},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2433272898197174},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15935352444648743},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13486188650131226},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.12019532918930054},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10692423582077026},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09226563572883606},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08682599663734436}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.8548642992973328},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.816727876663208},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.7632684111595154},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7114265561103821},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5819781422615051},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.560697615146637},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5576136112213135},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5446304082870483},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5413034558296204},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5184842944145203},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.495159775018692},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4361163377761841},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42997533082962036},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4286423325538635},{"id":"https://openalex.org/C173642442","wikidata":"https://www.wikidata.org/wiki/Q1253346","display_name":"Decimation","level":3,"score":0.41328057646751404},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4113900363445282},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4010372757911682},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.33208131790161133},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3261224329471588},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28224658966064453},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.26354092359542847},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2433272898197174},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15935352444648743},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13486188650131226},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.12019532918930054},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10692423582077026},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09226563572883606},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08682599663734436},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1973009.1973040","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1973009.1973040","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/630180","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/630180","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7900000214576721,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1839465939","https://openalex.org/W2024060531","https://openalex.org/W2065134004","https://openalex.org/W2103015818","https://openalex.org/W2120000030","https://openalex.org/W2121845560","https://openalex.org/W2142637184","https://openalex.org/W2161181105","https://openalex.org/W2161454431","https://openalex.org/W2545691991"],"related_works":["https://openalex.org/W2171793444","https://openalex.org/W2743305891","https://openalex.org/W1965232212","https://openalex.org/W3205162826","https://openalex.org/W2151657833","https://openalex.org/W4321510758","https://openalex.org/W2070693700","https://openalex.org/W1596716095","https://openalex.org/W2110346573","https://openalex.org/W4312327624"],"abstract_inverted_index":{"Current":[0],"EDA":[1],"tools":[2],"are":[3,19],"often":[4],"based":[5,71],"on":[6,72,90],"standard-cell":[7],"libraries":[8],"for":[9,38,55,96],"the":[10,26,82],"design":[11,53],"of":[12,64,93],"modern":[13],"complex":[14],"systems-on-chip.":[15],"In":[16],"general,":[17],"there":[18],"opposite":[20],"trends":[21],"to":[22,31,79],"compact":[23],"and":[24,30,62],"extend":[25],"standard":[27],"cell":[28,65],"libraries,":[29,35],"move":[32],"towards":[33],"custom":[34],"highly":[36],"optimized":[37],"specific":[39],"goals":[40],"(e.g.,":[41],"area,":[42],"timing":[43],"or":[44,47],"power":[45],"consumption)":[46],"designs.":[48],"We":[49],"thus":[50],"propose":[51],"a":[52,91,106],"methodology":[54,69],"library":[56],"sizing":[57],"that":[58],"combines":[59],"decimation":[60],"strategies":[61],"generation":[63],"variants.":[66],"The":[67,85],"proposed":[68],"is":[70],"Simulated":[73],"Annealing,":[74],"also":[75],"integrating":[76],"heuristic":[77],"principles":[78],"efficiently":[80],"guide":[81],"exploration":[83],"process.":[84],"approach":[86],"has":[87],"been":[88],"validated":[89],"set":[92],"common":[94],"benchmarks":[95],"logic":[97],"synthesis,":[98],"demonstrating":[99],"interesting":[100],"results,":[101],"specially":[102],"when":[103],"starting":[104],"from":[105],"relative":[107],"small":[108],"initial":[109],"library.":[110]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}