{"id":"https://openalex.org/W1996150371","doi":"https://doi.org/10.1145/1960397.1960408","title":"Synthesis of low power clock trees for handling power-supply variations","display_name":"Synthesis of low power clock trees for handling power-supply variations","publication_year":2011,"publication_date":"2011-03-22","ids":{"openalex":"https://openalex.org/W1996150371","doi":"https://doi.org/10.1145/1960397.1960408","mag":"1996150371"},"language":"en","primary_location":{"id":"doi:10.1145/1960397.1960408","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1960397.1960408","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 international symposium on Physical design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065909964","display_name":"Shashank Bujimalla","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shashank Bujimalla","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110204557","display_name":"Cheng\u2010Kok Koh","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng-Kok Koh","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5065909964"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":1.3248,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.81797429,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"37","last_page":"44"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8177329301834106},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7921806573867798},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7596050500869751},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6658794283866882},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6639511585235596},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5942978858947754},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5894410610198975},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5449936389923096},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5263544321060181},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.46949294209480286},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.44427254796028137},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.42204374074935913},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.41162538528442383},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19422465562820435},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13303717970848083},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13155648112297058},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.0909268856048584},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07648169994354248},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07341846823692322}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8177329301834106},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7921806573867798},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7596050500869751},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6658794283866882},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6639511585235596},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5942978858947754},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5894410610198975},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5449936389923096},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5263544321060181},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.46949294209480286},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.44427254796028137},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.42204374074935913},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41162538528442383},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19422465562820435},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13303717970848083},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13155648112297058},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0909268856048584},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07648169994354248},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07341846823692322},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1960397.1960408","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1960397.1960408","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 international symposium on Physical design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1507707340","https://openalex.org/W2002982872","https://openalex.org/W2021856858","https://openalex.org/W2032244362","https://openalex.org/W2041950850","https://openalex.org/W2102397043","https://openalex.org/W2108665876","https://openalex.org/W2109489242","https://openalex.org/W2112747772","https://openalex.org/W2115468286","https://openalex.org/W2125692303","https://openalex.org/W2127611603","https://openalex.org/W2170009145","https://openalex.org/W2478848959"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2617666058","https://openalex.org/W2803012234","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W3006003651","https://openalex.org/W2127892766","https://openalex.org/W2144282137"],"abstract_inverted_index":{"The":[0],"International":[1],"Symposium":[2],"on":[3,113],"Physical":[4],"Design":[5],"(ISPD)":[6],"2010":[7],"contest":[8,115],"presents":[9],"the":[10,34,41,64,101,140],"challenge":[11],"of":[12,47,66],"synthesizing":[13],"clock":[14,30,36,42,83,87,97,107,125],"distribution":[15],"networks":[16],"that":[17,50,76,122],"are":[18,51,104],"tolerant":[19],"to":[20,94],"severe":[21],"power-supply":[22],"and":[23],"wire-width":[24],"variations.":[25,67],"In":[26,68],"particular,":[27],"a":[28,54,59,73,91],"robust":[29],"network":[31],"should":[32],"satisfy":[33],"local":[35],"skew":[37,43],"(LCS)":[38],"constraint,":[39],"i.e.,":[40],"between":[44],"any":[45],"pair":[46],"sequential":[48],"elements":[49],"closer":[52],"than":[53],"user-specified":[55,60],"distance":[56],"is":[57],"below":[58],"limit,":[61],"even":[62,132],"in":[63,78,82,139],"presence":[65],"this":[69],"paper,":[70],"we":[71,134],"identify":[72],"few":[74],"factors":[75],"help":[77],"tolerating":[79],"these":[80],"variations":[81],"trees.":[84],"Our":[85,106],"proposed":[86],"tree":[88,108,126],"router":[89,109],"uses":[90],"two-stage":[92],"flow":[93],"construct":[95],"low-power":[96],"trees":[98],"for":[99],"which":[100],"LCS":[102],"constraints":[103],"met.":[105],"has":[110],"been":[111],"tested":[112],"ISPD'10":[114],"benchmark":[116],"circuits.":[117],"Extensive":[118],"Monte-Carlo":[119],"simulations":[120],"showed":[121],"low":[123],"power":[124],"solutions":[127],"could":[128],"effectively":[129],"handle":[130],"variations,":[131],"when":[133],"imposed":[135],"more":[136],"stringent":[137],"conditions":[138],"experimental":[141],"setup.":[142]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}