{"id":"https://openalex.org/W2075655993","doi":"https://doi.org/10.1145/1950413.1950468","title":"High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)","display_name":"High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)","publication_year":2011,"publication_date":"2011-02-27","ids":{"openalex":"https://openalex.org/W2075655993","doi":"https://doi.org/10.1145/1950413.1950468","mag":"2075655993"},"language":"en","primary_location":{"id":"doi:10.1145/1950413.1950468","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1950413.1950468","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079486968","display_name":"Sven van Haastregt","orcid":null},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Sven van Haastregt","raw_affiliation_strings":["Leiden University, Leiden, Netherlands"],"affiliations":[{"raw_affiliation_string":"Leiden University, Leiden, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014827775","display_name":"Stephen Neuendorffer","orcid":"https://orcid.org/0000-0003-2956-8428"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen Neuendorffer","raw_affiliation_strings":["Xilinx Research Labs, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Research Labs, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011464762","display_name":"Kees Vissers","orcid":"https://orcid.org/0000-0002-6249-315X"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kees Vissers","raw_affiliation_strings":["Xilinx Research Labs, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Research Labs, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064339872","display_name":"Bart Kienhuis","orcid":null},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Bart Kienhuis","raw_affiliation_strings":["Leiden University, Leiden, Netherlands"],"affiliations":[{"raw_affiliation_string":"Leiden University, Leiden, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5079486968"],"corresponding_institution_ids":["https://openalex.org/I121797337"],"apc_list":null,"apc_paid":null,"fwci":0.2519,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56017944,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"278","last_page":"278"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7996721863746643},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7917494773864746},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6555214524269104},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5448697209358215},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.49312397837638855},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4502500891685486},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4358872175216675},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4239358901977539},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.3953261375427246},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22980350255966187},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11245045065879822}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7996721863746643},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7917494773864746},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6555214524269104},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5448697209358215},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.49312397837638855},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4502500891685486},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4358872175216675},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4239358901977539},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.3953261375427246},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22980350255966187},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11245045065879822}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1950413.1950468","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1950413.1950468","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W1876592433","https://openalex.org/W2540393334","https://openalex.org/W2083269738","https://openalex.org/W1983570530","https://openalex.org/W2390042878","https://openalex.org/W2062932566","https://openalex.org/W2271847574"],"abstract_inverted_index":{"During":[0],"the":[1,16,81,163,169,173],"1990s,":[2],"High":[3],"Level":[4],"Synthesis":[5],"(HLS)":[6],"slowly":[7],"started":[8],"emerging":[9],"to":[10,13,56,118,136,150,168,185],"allow":[11],"designers":[12],"cope":[14],"with":[15,192],"ever-increasing":[17],"complexity":[18],"of":[19,33,39,84,88,109,142,162,172,198],"digital":[20],"signal":[21],"processing":[22],"systems":[23],"such":[24],"as":[25],"wireless":[26,90],"receivers.":[27],"Only":[28],"recently,":[29],"a":[30,85,89,100,106,119,152,178,196],"new":[31],"generation":[32],"high-quality":[34],"commercial":[35],"HLS":[36,96,116,132,154,180,193],"tools":[37,52,68],"capable":[38],"generating":[40],"decent":[41],"RTL":[42,125,209],"architectures":[43,191],"from":[44],"algorithmic-style":[45],"code":[46],"has":[47],"become":[48],"available.":[49],"Although":[50],"these":[51,67],"are":[53],"now":[54],"starting":[55],"be":[57],"adopted":[58],"for":[59,66],"actual":[60],"designs,":[61],"detailed":[62],"experiences":[63],"and":[64,105,144,158,187],"results":[65],"in":[69,140,194,204],"significant":[70,86,202],"designs":[71],"is":[72,134,166],"still":[73],"lacking.":[74],"In":[75],"this":[76,137],"work":[77],"we":[78,182],"have":[79,113],"analyzed":[80],"design":[82,126,170,205],"process":[83],"portion":[87],"communication":[91],"application":[92,190],"using":[93,123],"AutoESL's":[94],"AutoPilot":[95],"tool.":[97],"We":[98,112,128],"target":[99],"Xilinx":[101],"Virtex-5":[102],"FPGA":[103],"device":[104],"clock":[107],"frequency":[108],"225":[110],"MHz.":[111],"compared":[114],"our":[115,131],"implementation":[117,121,133,139,155,165],"reference":[120,138,164,174],"obtained":[122],"manual":[124,208],"methods.":[127],"found":[129],"that":[130],"competitive":[135],"terms":[141],"throughput":[143,157],"resource":[145,159],"cost.":[146],"The":[147],"time":[148,171,206],"needed":[149],"obtain":[151],"first":[153,179],"matching":[156],"cost":[160],"aspects":[161],"similar":[167],"implementation.":[175],"After":[176],"obtaining":[177],"implementation,":[181],"were":[183],"able":[184],"explore":[186],"implement":[188],"different":[189],"only":[195],"couple":[197],"hours,":[199],"thereby":[200],"gaining":[201],"savings":[203],"over":[207],"design,":[210],"where":[211],"architectural":[212],"exploration":[213],"may":[214],"take":[215],"weeks.":[216]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}