{"id":"https://openalex.org/W2080270089","doi":"https://doi.org/10.1145/1950413.1950443","title":"Towards scalable FPGA CAD through architecture","display_name":"Towards scalable FPGA CAD through architecture","publication_year":2011,"publication_date":"2011-02-27","ids":{"openalex":"https://openalex.org/W2080270089","doi":"https://doi.org/10.1145/1950413.1950443","mag":"2080270089"},"language":"en","primary_location":{"id":"doi:10.1145/1950413.1950443","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1950413.1950443","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042976080","display_name":"Scott Y. L. Chin","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Scott Y.L. Chin","raw_affiliation_strings":["University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J.E. Wilton","raw_affiliation_strings":["University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":3.1325,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.91828813,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"143","last_page":"152"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9041626453399658},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7481456995010376},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7454831004142761},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7100692987442017},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.632307231426239},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.5965258479118347},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5621267557144165},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4869164228439331},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4741092324256897},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46140992641448975},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.4340824484825134},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4190351366996765},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20151445269584656},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15661272406578064}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9041626453399658},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7481456995010376},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7454831004142761},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7100692987442017},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.632307231426239},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.5965258479118347},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5621267557144165},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4869164228439331},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4741092324256897},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46140992641448975},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.4340824484825134},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4190351366996765},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20151445269584656},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15661272406578064},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1950413.1950443","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1950413.1950443","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.225.109","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.225.109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/%7Estevew/papers/pdf/fpga2011a.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.6200000047683716}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1522095270","https://openalex.org/W1523051745","https://openalex.org/W2003258276","https://openalex.org/W2004015744","https://openalex.org/W2005275470","https://openalex.org/W2008531154","https://openalex.org/W2023462222","https://openalex.org/W2023788229","https://openalex.org/W2024701359","https://openalex.org/W2035847677","https://openalex.org/W2039288205","https://openalex.org/W2062435236","https://openalex.org/W2069345435","https://openalex.org/W2095558812","https://openalex.org/W2096185144","https://openalex.org/W2113645429","https://openalex.org/W2115402073","https://openalex.org/W2127309005","https://openalex.org/W2138840350","https://openalex.org/W2142613770","https://openalex.org/W2151872233","https://openalex.org/W2163599210","https://openalex.org/W2282645074","https://openalex.org/W3141004699"],"related_works":["https://openalex.org/W2371266106","https://openalex.org/W2998132311","https://openalex.org/W2117382851","https://openalex.org/W3006505070","https://openalex.org/W2382449560","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W2767298477","https://openalex.org/W2332075903","https://openalex.org/W1579891439"],"abstract_inverted_index":{"Long":[0],"FPGA":[1,14],"CAD":[2],"runtime":[3],"has":[4],"emerged":[5],"as":[6,34],"a":[7,23,39],"limitation":[8],"to":[9,42],"the":[10,20,28],"future":[11],"scaling":[12,47],"of":[13,22,48],"densities.":[15],"Already,":[16],"compile":[17,44],"times":[18],"on":[19],"order":[21],"day":[24],"are":[25],"common,":[26],"and":[27],"situation":[29],"will":[30,50],"only":[31],"get":[32,36],"worse":[33],"FPGAs":[35,49],"larger.":[37],"Without":[38],"concerted":[40],"effort":[41],"reduce":[43],"times,":[45],"further":[46],"eventually":[51],"become":[52],"impractical.":[53]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
