{"id":"https://openalex.org/W2083695406","doi":"https://doi.org/10.1145/1926367.1926381","title":"Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation","display_name":"Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation","publication_year":2010,"publication_date":"2010-09-14","ids":{"openalex":"https://openalex.org/W2083695406","doi":"https://doi.org/10.1145/1926367.1926381","mag":"2083695406"},"language":"en","primary_location":{"id":"doi:10.1145/1926367.1926381","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1926367.1926381","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081752237","display_name":"Kentaro Sano","orcid":"https://orcid.org/0000-0002-6681-4192"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Kentaro Sano","raw_affiliation_strings":["Tohoku University, Sendai, Japan","Tohoku University Sendai, Japan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tohoku University, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Tohoku University Sendai, Japan#TAB#","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085874089","display_name":"Luzhou Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Luzhou Wang","raw_affiliation_strings":["Tohoku University, Sendai, Japan","Tohoku University Sendai, Japan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tohoku University, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Tohoku University Sendai, Japan#TAB#","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101413965","display_name":"Satoru Yamamoto","orcid":"https://orcid.org/0000-0003-1431-3035"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Satoru Yamamoto","raw_affiliation_strings":["Tohoku University, Sendai, Japan","Tohoku University Sendai, Japan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tohoku University, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Tohoku University Sendai, Japan#TAB#","institution_ids":["https://openalex.org/I201537933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5081752237"],"corresponding_institution_ids":["https://openalex.org/I201537933"],"apc_list":null,"apc_paid":null,"fwci":1.0114,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.78024737,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"38","issue":"4","first_page":"80","last_page":"86"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.8956000804901123},{"id":"https://openalex.org/keywords/stencil","display_name":"Stencil","score":0.816189169883728},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7734299898147583},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7721221446990967},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7516872882843018},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6630982160568237},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.661712646484375},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.590205192565918},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4891205430030823},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.48774272203445435},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.4567878842353821},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34497037529945374},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.28694307804107666},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.27173590660095215},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27155154943466187},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14044460654258728},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12612703442573547},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07636433839797974}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.8956000804901123},{"id":"https://openalex.org/C76752949","wikidata":"https://www.wikidata.org/wiki/Q7607499","display_name":"Stencil","level":2,"score":0.816189169883728},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7734299898147583},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7721221446990967},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7516872882843018},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6630982160568237},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.661712646484375},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.590205192565918},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4891205430030823},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.48774272203445435},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.4567878842353821},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34497037529945374},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28694307804107666},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.27173590660095215},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27155154943466187},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14044460654258728},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12612703442573547},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07636433839797974},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1926367.1926381","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1926367.1926381","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W13759931","https://openalex.org/W1939837620","https://openalex.org/W1987243435","https://openalex.org/W1989336131","https://openalex.org/W1994266431","https://openalex.org/W2002555321","https://openalex.org/W2017369466","https://openalex.org/W2021748565","https://openalex.org/W2097586424","https://openalex.org/W2106521816","https://openalex.org/W2112980698","https://openalex.org/W2114393091","https://openalex.org/W2117638260","https://openalex.org/W2130048397","https://openalex.org/W2136268150","https://openalex.org/W2150405043","https://openalex.org/W2154786353","https://openalex.org/W2154815337","https://openalex.org/W2158087462","https://openalex.org/W2294887632","https://openalex.org/W2911830835"],"related_works":["https://openalex.org/W2154055002","https://openalex.org/W4200123712","https://openalex.org/W3122909934","https://openalex.org/W2804132206","https://openalex.org/W1965512548","https://openalex.org/W1531780705","https://openalex.org/W2370911386","https://openalex.org/W2116951845","https://openalex.org/W2132758316","https://openalex.org/W2083695406"],"abstract_inverted_index":{"This":[0],"paper":[1],"demonstrates":[2,82],"and":[3,7,36,40],"evaluates":[4],"the":[5,8,11,30,38,41,56,84,92,117,124,132],"performance":[6,129],"scalability":[9],"of":[10,25,33,43,55,111,134],"systolic":[12],"computational-memory":[13],"array":[14,69],"(SCMA)":[15],"for":[16],"stencil":[17],"computation,":[18],"which":[19,64],"is":[20],"a":[21,53,66],"typical":[22,112],"computing":[23,113],"kernel":[24],"scientific":[26],"simulation.":[27],"We":[28,51],"describe":[29],"basic":[31],"architecture":[32],"th":[34],"SCMA,":[35],"show":[37,122],"requirements":[39],"design":[42],"SCMAs":[44],"to":[45,102,131],"scalably":[46],"operate":[47],"over":[48],"multiple":[49],"devices.":[50],"implement":[52],"prototype":[54,80],"SCMA":[57,81],"with":[58,75],"three":[59,72,108],"ALTERA":[60],"Stratix":[61],"III":[62],"FPGAs,":[63],"form":[65],"1--3":[67],"FPGA":[68],"by":[70],"conecting":[71],"DE3":[73],"boards":[74],"different":[76,105],"clock":[77,88],"sources.":[78],"The":[79],"that":[83,123],"difference":[85,119],"in":[86,137],"operating":[87],"frequency":[89],"hardly":[90],"influences":[91],"total":[93],"execution":[94],"cycles":[95,101],"while":[96],"it":[97],"slightly":[98],"causes":[99],"stall":[100],"sub-SCMAs":[103],"on":[104,116],"FPGAs.":[106],"With":[107],"banchmark":[109],"programs":[110],"kernels":[114],"based":[115],"finite":[118],"method,":[120],"we":[121],"increased":[125],"FPGAs":[126],"provide":[127],"higher":[128],"proportional":[130],"number":[133],"devices,":[135],"resulting":[136],"almost":[138],"linear":[139],"speedup.":[140]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
