{"id":"https://openalex.org/W1973845444","doi":"https://doi.org/10.1145/1880043.1880044","title":"Impact of high-level transformations within the ROCCC framework","display_name":"Impact of high-level transformations within the ROCCC framework","publication_year":2010,"publication_date":"2010-12-01","ids":{"openalex":"https://openalex.org/W1973845444","doi":"https://doi.org/10.1145/1880043.1880044","mag":"1973845444"},"language":"en","primary_location":{"id":"doi:10.1145/1880043.1880044","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1880043.1880044","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1880043.1880044","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/1880043.1880044","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016761040","display_name":"Betul Buyukkurt","orcid":null},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Betul Buyukkurt","raw_affiliation_strings":["University of California, Riverside, Riverside, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Riverside, Riverside, CA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040248917","display_name":"John Cortes","orcid":null},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Cortes","raw_affiliation_strings":["University of California, Riverside, Riverside, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Riverside, Riverside, CA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012012492","display_name":"Jason Villarreal","orcid":null},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Villarreal","raw_affiliation_strings":["University of California, Riverside, Riverside, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Riverside, Riverside, CA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033921328","display_name":"Walid Najjar","orcid":"https://orcid.org/0000-0001-6761-6801"},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Walid A. Najjar","raw_affiliation_strings":["University of California, Riverside, Riverside, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Riverside, Riverside, CA","institution_ids":["https://openalex.org/I103635307"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I103635307"],"apc_list":null,"apc_paid":null,"fwci":1.497,"has_fulltext":true,"cited_by_count":18,"citation_normalized_percentile":{"value":0.82750428,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"7","issue":"4","first_page":"1","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8719907999038696},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8191980123519897},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6157534718513489},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6017880439758301},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5766637325286865},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5723602771759033},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5368222594261169},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5100460648536682},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47487160563468933},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.4644154906272888},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.43985283374786377},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.4105861783027649},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.18473634123802185},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10500586032867432}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8719907999038696},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8191980123519897},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6157534718513489},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6017880439758301},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5766637325286865},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5723602771759033},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5368222594261169},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5100460648536682},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47487160563468933},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.4644154906272888},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.43985283374786377},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.4105861783027649},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.18473634123802185},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10500586032867432},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1880043.1880044","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1880043.1880044","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1880043.1880044","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.429.2558","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.429.2558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.ucr.edu/~najjar/papers/2010/ACM-TACO-2010.pdf","raw_type":"text"}],"best_oa_location":{"id":"doi:10.1145/1880043.1880044","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1880043.1880044","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1880043.1880044","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1973845444.pdf","grobid_xml":"https://content.openalex.org/works/W1973845444.grobid-xml"},"referenced_works_count":25,"referenced_works":["https://openalex.org/W1568192366","https://openalex.org/W1596289985","https://openalex.org/W1686420892","https://openalex.org/W1843505774","https://openalex.org/W1954746259","https://openalex.org/W1974169079","https://openalex.org/W1989435461","https://openalex.org/W2013286553","https://openalex.org/W2034248530","https://openalex.org/W2051498260","https://openalex.org/W2097265665","https://openalex.org/W2098420952","https://openalex.org/W2103581911","https://openalex.org/W2112432448","https://openalex.org/W2122128838","https://openalex.org/W2139548488","https://openalex.org/W2145947338","https://openalex.org/W2150813948","https://openalex.org/W2160342394","https://openalex.org/W2167408328","https://openalex.org/W2170675383","https://openalex.org/W2293374899","https://openalex.org/W2404756046","https://openalex.org/W4231605864","https://openalex.org/W4253757365"],"related_works":["https://openalex.org/W1853049011","https://openalex.org/W2069811640","https://openalex.org/W2091716239","https://openalex.org/W1547259518","https://openalex.org/W2113648965","https://openalex.org/W2347401507","https://openalex.org/W2158819012","https://openalex.org/W2389852039","https://openalex.org/W2591834580","https://openalex.org/W1973845444"],"abstract_inverted_index":{"Reconfigurable":[0],"computers,":[1],"where":[2],"one":[3],"or":[4],"more":[5],"FPGAs":[6,32,71,84],"are":[7,13,33,61],"attached":[8],"to":[9,47,52,64,161,169,176,179,189,197],"a":[10,92,99],"conventional":[11],"microprocessor,":[12],"promising":[14],"platforms":[15],"for":[16,31,70,83,127],"code":[17,126],"acceleration.":[18],"Despite":[19],"their":[20],"advantages,":[21],"programmability":[22],"concerns":[23],"and":[24,45,50,67,79,122,130,134,193],"the":[25,35,54,65,87,111,124,140,147,150,191],"lack":[26],"of":[27,77,101,142,149,174,200,214,217],"efficient":[28],"design":[29],"tools/compilers":[30],"preventing":[34],"technology's":[36],"widespread":[37],"adoption.":[38],"The":[39,59,202],"traditional":[40],"compiler":[41,108],"technology":[42],"is":[43,104],"microprocessor-based-systems-specific":[44],"needs":[46,55],"be":[48],"customized":[49],"augmented":[51],"address":[53],"in":[56,89,96],"reconfigurable":[57,112],"computing.":[58],"challenges":[60],"several":[62,117,157],"due":[63],"resources":[66],"performance":[68,148],"constraints":[69],"being":[72],"drastically":[73],"different":[74],"than":[75,95],"those":[76],"microprocessors,":[78],"also":[80],"that":[81,120],"compiling":[82],"requires":[85],"laying":[86],"computation":[88,220],"space":[90],"by":[91,98],"circuit":[93,171,180],"rather":[94],"time":[97],"sequence":[100],"instructions.":[102],"ROCCC":[103,115,154,207],"an":[105],"optimizing":[106],"C-to-VHDL":[107],"specifically":[109],"targeting":[110],"computer":[113],"platforms.":[114],"includes":[116],"high-level":[118,144],"optimizations":[119,160,168,188],"parallelize":[121],"optimize":[123],"source":[125],"minimized":[128],"area":[129,172],"critical":[131],"path":[132],"length":[133],"maximized":[135],"throughput.":[136],"This":[137],"article":[138],"presents":[139],"effect":[141],"ROCCC's":[143],"transformations":[145,195],"on":[146],"generated":[151,182],"VHDL":[152],"output.":[153],"utilizes:":[155],"(1)":[156],"array":[158],"access":[159],"eliminate":[162],"redundant":[163],"memory":[164],"accesses,":[165],"(2)":[166],"procedure-level":[167],"achieve":[170],"reductions":[173],"up":[175],"88%":[177],"compared":[178],"areas":[181],"from":[183],"unoptimized":[184],"codes,":[185],"(3)":[186],"loop-level":[187],"increase":[190],"throughput,":[192],"(4)":[194],"unique":[196],"certain":[198],"classes":[199],"applications.":[201],"preceding":[203],"listed":[204],"features":[205],"help":[206],"generate":[208],"circuits":[209],"with":[210],"very":[211,218],"large":[212],"degrees":[213],"parallelism":[215],"capable":[216],"high":[219],"rates.":[221]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":4}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
