{"id":"https://openalex.org/W2170167304","doi":"https://doi.org/10.1145/1878921.1878939","title":"A memory interface for multi-purpose multi-stream accelerators","display_name":"A memory interface for multi-purpose multi-stream accelerators","publication_year":2010,"publication_date":"2010-10-24","ids":{"openalex":"https://openalex.org/W2170167304","doi":"https://doi.org/10.1145/1878921.1878939","mag":"2170167304"},"language":"en","primary_location":{"id":"doi:10.1145/1878921.1878939","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1878921.1878939","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047953495","display_name":"Sylvain Girbal","orcid":"https://orcid.org/0009-0008-7620-9069"},"institutions":[{"id":"https://openalex.org/I4210140930","display_name":"Thales (France)","ror":"https://ror.org/04emwm605","country_code":"FR","type":"company","lineage":["https://openalex.org/I4210140930"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Sylvain Girbal","raw_affiliation_strings":["Thales Research and Technology, Palaiseau, France"],"affiliations":[{"raw_affiliation_string":"Thales Research and Technology, Palaiseau, France","institution_ids":["https://openalex.org/I4210140930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040252809","display_name":"Olivier Temam","orcid":null},"institutions":[{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en informatique et en automatique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1326498283"]},{"id":"https://openalex.org/I4210126360","display_name":"Inria Saclay - \u00cele de France","ror":"https://ror.org/0315e5x55","country_code":"FR","type":"government","lineage":["https://openalex.org/I1326498283","https://openalex.org/I4210126360"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Olivier Temam","raw_affiliation_strings":["INRIA Saclay, Orsay, France"],"affiliations":[{"raw_affiliation_string":"INRIA Saclay, Orsay, France","institution_ids":["https://openalex.org/I4210126360","https://openalex.org/I1326498283"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026413671","display_name":"Sami Yehia","orcid":null},"institutions":[{"id":"https://openalex.org/I4210140930","display_name":"Thales (France)","ror":"https://ror.org/04emwm605","country_code":"FR","type":"company","lineage":["https://openalex.org/I4210140930"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Sami Yehia","raw_affiliation_strings":["Thales Research and Technology, Palaiseau, France"],"affiliations":[{"raw_affiliation_string":"Thales Research and Technology, Palaiseau, France","institution_ids":["https://openalex.org/I4210140930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021999741","display_name":"Hugues Berry","orcid":"https://orcid.org/0000-0003-3470-683X"},"institutions":[{"id":"https://openalex.org/I4210126360","display_name":"Inria Saclay - \u00cele de France","ror":"https://ror.org/0315e5x55","country_code":"FR","type":"government","lineage":["https://openalex.org/I1326498283","https://openalex.org/I4210126360"]},{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en informatique et en automatique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1326498283"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Hugues Berry","raw_affiliation_strings":["INRIA Saclay, Orsay, France"],"affiliations":[{"raw_affiliation_string":"INRIA Saclay, Orsay, France","institution_ids":["https://openalex.org/I4210126360","https://openalex.org/I1326498283"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100415036","display_name":"Zheng Li","orcid":"https://orcid.org/0000-0002-9704-7651"},"institutions":[{"id":"https://openalex.org/I4210126360","display_name":"Inria Saclay - \u00cele de France","ror":"https://ror.org/0315e5x55","country_code":"FR","type":"government","lineage":["https://openalex.org/I1326498283","https://openalex.org/I4210126360"]},{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en informatique et en automatique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1326498283"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Zheng LI","raw_affiliation_strings":["INRIA Saclay, Orsay, France"],"affiliations":[{"raw_affiliation_string":"INRIA Saclay, Orsay, France","institution_ids":["https://openalex.org/I4210126360","https://openalex.org/I1326498283"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5047953495"],"corresponding_institution_ids":["https://openalex.org/I4210140930"],"apc_list":null,"apc_paid":null,"fwci":0.7491,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.75108413,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"107","last_page":"116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8521802425384521},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5671878457069397},{"id":"https://openalex.org/keywords/predictability","display_name":"Predictability","score":0.5246168375015259},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5104559659957886},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49953317642211914},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49049681425094604},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4771237373352051},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4371569752693176},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4363701343536377},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.41826778650283813},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27492135763168335},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.229214608669281},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22271844744682312}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8521802425384521},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5671878457069397},{"id":"https://openalex.org/C197640229","wikidata":"https://www.wikidata.org/wiki/Q2534066","display_name":"Predictability","level":2,"score":0.5246168375015259},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5104559659957886},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49953317642211914},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49049681425094604},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4771237373352051},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4371569752693176},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4363701343536377},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.41826778650283813},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27492135763168335},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.229214608669281},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22271844744682312},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1878921.1878939","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1878921.1878939","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.4300000071525574,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1677745057","https://openalex.org/W1890303118","https://openalex.org/W2105778948","https://openalex.org/W2116361585","https://openalex.org/W2128938762","https://openalex.org/W2136262589","https://openalex.org/W2137653322","https://openalex.org/W2141389982","https://openalex.org/W2143285027","https://openalex.org/W2144133815","https://openalex.org/W2145285494","https://openalex.org/W2147877714","https://openalex.org/W2149590159","https://openalex.org/W2167013139","https://openalex.org/W2168923722","https://openalex.org/W2169150396","https://openalex.org/W2171006257","https://openalex.org/W2275849925","https://openalex.org/W2917252586","https://openalex.org/W3141428879","https://openalex.org/W4234370346","https://openalex.org/W4255807648"],"related_works":["https://openalex.org/W2726467123","https://openalex.org/W2064726690","https://openalex.org/W4252678288","https://openalex.org/W4254065731","https://openalex.org/W1607297154","https://openalex.org/W4210820789","https://openalex.org/W2078379271","https://openalex.org/W2043460294","https://openalex.org/W4210712718","https://openalex.org/W1905398909"],"abstract_inverted_index":{"Power":[0],"and":[1,10,45,58,99,135],"programming":[2],"challenges":[3],"make":[4],"heterogeneous":[5],"multi-cores":[6],"composed":[7],"of":[8,75,86,102,123,129,140,147,158],"cores":[9],"ASICs":[11],"an":[12,26,163],"attractive":[13,28],"alternative":[14],"to":[15,56,93,110],"homogeneous":[16],"multi-cores.":[17],"Recently,":[18],"multi-purpose":[19,116],"loop-based":[20,167],"generated":[21,166],"accelerators":[22,77,117],"have":[23,32],"emerged":[24],"as":[25,82,84],"especially":[27],"accelerator":[29,168],"option.":[30],"They":[31],"several":[33],"assets:":[34],"short":[35],"design":[36,111],"time":[37],"(automatic":[38],"generation),":[39],"flexibility":[40],"(multi-purpose)":[41],"but":[42],"low":[43],"configuration":[44],"routing":[46],"overhead":[47],"(unlike":[48],"FPGAs),":[49],"computational":[50],"performance":[51],"(operations":[52],"are":[53],"directly":[54],"mapped":[55],"hardware),":[57],"a":[59,112,138,155],"focus":[60],"on":[61],"memory":[62,73,96,113,130,160],"throughput":[63,100],"by":[64,143],"leveraging":[65,144],"loop":[66],"constructs.":[67],"However,":[68],"with":[69,154],"multiple":[70],"streams,":[71],"the":[72,95,120,145,152,159],"behavior":[74],"such":[76],"can":[78],"become":[79],"at":[80],"least":[81],"complex":[83,133],"that":[85],"superscalar":[87],"processors,":[88,134],"while":[89],"they":[90],"still":[91],"need":[92],"retain":[94],"ordering":[97,121],"predictability":[98,122],"efficiency":[101,127],"DMAs.":[103],"In":[104],"this":[105],"article,":[106],"we":[107],"show":[108],"how":[109],"interface":[114,161],"for":[115,132,162],"which":[118],"combines":[119],"DMAs,":[124],"retains":[125],"key":[126],"features":[128],"systems":[131],"requires":[136],"only":[137],"fraction":[139],"their":[141],"cost":[142],"properties":[146],"streams":[148],"references.":[149],"We":[150],"evaluate":[151],"approach":[153],"synthesizable":[156],"version":[157],"example":[164],"9-task":[165]},"counts_by_year":[{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}