{"id":"https://openalex.org/W2082116297","doi":"https://doi.org/10.1145/1854273.1854339","title":"On-chip network design considerations for compute accelerators","display_name":"On-chip network design considerations for compute accelerators","publication_year":2010,"publication_date":"2010-09-11","ids":{"openalex":"https://openalex.org/W2082116297","doi":"https://doi.org/10.1145/1854273.1854339","mag":"2082116297"},"language":"en","primary_location":{"id":"doi:10.1145/1854273.1854339","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1854273.1854339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037238310","display_name":"Ali Bakhoda","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ali Bakhoda","raw_affiliation_strings":["University of British Columbia, Canada, BC, Canada","University of British Columbia, Department of Electrical and Computer Engineering, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"University of British Columbia, Canada, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"University of British Columbia, Department of Electrical and Computer Engineering, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100698124","display_name":"John Kim","orcid":"https://orcid.org/0000-0003-3958-3891"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"John Kim","raw_affiliation_strings":["KAIST, Daejeon, South Korea","KAIST, Department of Computer Science, Daejeon, Korea"],"affiliations":[{"raw_affiliation_string":"KAIST, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"KAIST, Department of Computer Science, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026788167","display_name":"Tor M. Aamodt","orcid":"https://orcid.org/0000-0003-1161-692X"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Tor M. Aamodt","raw_affiliation_strings":["University of British Columbia, Vancouver, BC, Canada","University of British Columbia, Department of Electrical and Computer Engineering, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"University of British Columbia, Department of Electrical and Computer Engineering, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037238310"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.1780437,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"535","last_page":"536"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.989300012588501,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8428497314453125},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6172163486480713},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.515433669090271},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.4998502731323242},{"id":"https://openalex.org/keywords/infiniband","display_name":"InfiniBand","score":0.4803134799003601},{"id":"https://openalex.org/keywords/network-interface-controller","display_name":"Network interface controller","score":0.44512224197387695},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.4271789789199829},{"id":"https://openalex.org/keywords/network-architecture","display_name":"Network architecture","score":0.4207262694835663},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41714394092559814},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4110427796840668},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.40777552127838135},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38644254207611084},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37319517135620117},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21517175436019897},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11979979276657104}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8428497314453125},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6172163486480713},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.515433669090271},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.4998502731323242},{"id":"https://openalex.org/C2781030343","wikidata":"https://www.wikidata.org/wiki/Q922437","display_name":"InfiniBand","level":2,"score":0.4803134799003601},{"id":"https://openalex.org/C171659815","wikidata":"https://www.wikidata.org/wiki/Q165233","display_name":"Network interface controller","level":2,"score":0.44512224197387695},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.4271789789199829},{"id":"https://openalex.org/C193415008","wikidata":"https://www.wikidata.org/wiki/Q639681","display_name":"Network architecture","level":2,"score":0.4207262694835663},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41714394092559814},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4110427796840668},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.40777552127838135},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38644254207611084},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37319517135620117},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21517175436019897},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11979979276657104}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1854273.1854339","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1854273.1854339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.472.133","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.472.133","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"https://www.ece.ubc.ca/~aamodt/papers/bakhoda.pact2010.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1979527452"],"related_works":["https://openalex.org/W1977425666","https://openalex.org/W2148030923","https://openalex.org/W2169866068","https://openalex.org/W2508635599","https://openalex.org/W2007275081","https://openalex.org/W2134172439","https://openalex.org/W1979573153","https://openalex.org/W1603420497","https://openalex.org/W2121956647","https://openalex.org/W2269927805"],"abstract_inverted_index":{"There":[0],"has":[1],"been":[2],"little":[3],"work":[4],"investigating":[5],"the":[6,39,69,92,93,99,109,139,150,157],"overall":[7],"performance":[8,22,51],"impact":[9],"of":[10,23,33,52,72,85,95,138],"on-chip":[11,82,119],"communication":[12,70,137],"in":[13],"manycore":[14],"compute":[15,26,34],"accelerators.":[16],"In":[17,112],"this":[18],"paper":[19],"we":[20,49,90,114],"evaluate":[21],"a":[24,53,57,77,116,145],"GPU-like":[25],"accelerator":[27],"running":[28],"CUDA":[29],"workloads":[30],"and":[31,38,126],"consisting":[32],"nodes,":[35],"interconnection":[36],"network":[37,120,132,152],"graphics":[40],"DRAM":[41],"memory":[42,100],"system":[43],"using":[44],"detailed":[45],"cycle-level":[46],"simulation.":[47],"First,":[48],"study":[50],"baseline":[54],"architecture":[55],"employing":[56],"scalable":[58],"mesh":[59],"network.":[60,83],"We":[61,143],"then":[62],"propose":[63,115],"several":[64],"microarchitectural":[65],"techniques":[66],"to":[67,104],"exploit":[68],"characteristics":[71],"these":[73],"applications":[74],"while":[75],"providing":[76],"cost-effective":[78],"(i.e.,":[79],"low":[80],"area)":[81],"Instead":[84],"increasing":[86],"costly":[87],"bisection":[88],"bandwidth,":[89],"increase":[91,105,156],"number":[94],"injection":[96],"ports":[97],"at":[98,108],"controller":[101],"router":[102],"nodes":[103],"terminal":[106],"bandwidth":[107],"few":[110],"nodes.":[111],"addition,":[113],"novel":[117],"\"checkerboard\"":[118],"which":[121],"alternates":[122],"between":[123],"conventional,":[124],"full-routers":[125],"half-routers":[127],"with":[128],"limited":[129,136],"connectivity.":[130],"This":[131],"is":[133],"enabled":[134],"by":[135],"many-to-few":[140],"traffic":[141],"pattern.":[142],"describe":[144],"minimal":[146],"routing":[147],"algorithm":[148],"for":[149],"checkerboard":[151],"that":[153],"does":[154],"not":[155],"hop":[158],"count.":[159]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
