{"id":"https://openalex.org/W1972995899","doi":"https://doi.org/10.1145/1839667.1839671","title":"Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors","display_name":"Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W1972995899","doi":"https://doi.org/10.1145/1839667.1839671","mag":"1972995899"},"language":"en","primary_location":{"id":"doi:10.1145/1839667.1839671","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1839667.1839671","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1839667.1839671","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/1839667.1839671","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081739050","display_name":"Ryan Rakvic","orcid":null},"institutions":[{"id":"https://openalex.org/I189158971","display_name":"United States Naval Academy","ror":"https://ror.org/00znex860","country_code":"US","type":"education","lineage":["https://openalex.org/I1330347796","https://openalex.org/I189158971","https://openalex.org/I3130687028"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Rakvic","raw_affiliation_strings":["United States Naval Academy, Annapolis, MD"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"United States Naval Academy, Annapolis, MD","institution_ids":["https://openalex.org/I189158971"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113219580","display_name":"Qian Cai","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Q. Cai","raw_affiliation_strings":["Intel Labs-UPC, Barcelona, Spain","Intel Labs, UPC, Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs-UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Intel Labs, UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102999739","display_name":"J. M. Gonzalez Castro","orcid":"https://orcid.org/0000-0003-0199-3158"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Gonz\u00e1lez","raw_affiliation_strings":["Intel Labs-UPC, Barcelona, Spain","Intel Labs, UPC, Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs-UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Intel Labs, UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000686736","display_name":"Grigorios Magklis","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"G. Magklis","raw_affiliation_strings":["Intel Labs-UPC, Barcelona, Spain","Intel Labs, UPC, Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs-UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Intel Labs, UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111728780","display_name":"Pedro Chaparro","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"P. Chaparro","raw_affiliation_strings":["Intel Labs-UPC, Barcelona, Spain","Intel Labs, UPC, Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs-UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Intel Labs, UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100733331","display_name":"Antonio Gonz\u00e1lez","orcid":"https://orcid.org/0000-0002-0009-0996"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. Gonz\u00e1lez","raw_affiliation_strings":["Intel Labs-UPC, Barcelona, Spain","Intel Labs, UPC, Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs-UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Intel Labs, UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":5,"citation_normalized_percentile":{"value":0.06728625,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"7","issue":"2","first_page":"1","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.9055390357971191},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8136473894119263},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7064974308013916},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.6322786211967468},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6191875338554382},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.5273528695106506},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43817001581192017},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.399395227432251},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.35628262162208557},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07738476991653442},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06905171275138855}],"concepts":[{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.9055390357971191},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8136473894119263},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7064974308013916},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.6322786211967468},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6191875338554382},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.5273528695106506},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43817001581192017},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.399395227432251},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.35628262162208557},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07738476991653442},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06905171275138855}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1839667.1839671","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1839667.1839671","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1839667.1839671","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/1839667.1839671","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1839667.1839671","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1839667.1839671","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1972995899.pdf","grobid_xml":"https://content.openalex.org/works/W1972995899.grobid-xml"},"referenced_works_count":38,"referenced_works":["https://openalex.org/W20828189","https://openalex.org/W73121609","https://openalex.org/W79022431","https://openalex.org/W1587466478","https://openalex.org/W1702275516","https://openalex.org/W1934130410","https://openalex.org/W1981411441","https://openalex.org/W2003061490","https://openalex.org/W2022740893","https://openalex.org/W2052006175","https://openalex.org/W2054989520","https://openalex.org/W2079186079","https://openalex.org/W2098540801","https://openalex.org/W2102727118","https://openalex.org/W2106149957","https://openalex.org/W2108387401","https://openalex.org/W2112067212","https://openalex.org/W2112085716","https://openalex.org/W2118532220","https://openalex.org/W2131308327","https://openalex.org/W2132100607","https://openalex.org/W2137055485","https://openalex.org/W2140057257","https://openalex.org/W2141242940","https://openalex.org/W2145815796","https://openalex.org/W2147943147","https://openalex.org/W2148528597","https://openalex.org/W2150547581","https://openalex.org/W2153173314","https://openalex.org/W2158599369","https://openalex.org/W2162847528","https://openalex.org/W2170653240","https://openalex.org/W2171703369","https://openalex.org/W2535431417","https://openalex.org/W4239012550","https://openalex.org/W4239331546","https://openalex.org/W4240807263","https://openalex.org/W4242466841"],"related_works":["https://openalex.org/W2115561485","https://openalex.org/W1985089255","https://openalex.org/W2153202644","https://openalex.org/W2010970156","https://openalex.org/W2105895556","https://openalex.org/W2482815832","https://openalex.org/W4235861380","https://openalex.org/W2377593213","https://openalex.org/W2294358097","https://openalex.org/W2733115356"],"abstract_inverted_index":{"We":[0,86,126],"provide":[1,53,87],"an":[2,54,83,118,133],"analysis":[3],"of":[4,43,57,82,91],"thread-management":[5],"techniques":[6],"that":[7,121],"increase":[8,157],"performance":[9,69,92,97,106,152,158],"or":[10,161],"reduce":[11,123,143,163],"energy":[12,23,124,144,164],"in":[13,78],"multicore":[14],"and":[15,41,99],"Simultaneous":[16],"Multithreaded":[17],"(SMT)":[18],"cores.":[19],"Thread":[20,65,140,154],"delaying":[21,59,141],"reduces":[22],"consumption":[24,145,165],"by":[25,70,146,159,166],"running":[26,137],"the":[27,30,39,44,75,79],"core":[28,120],"containing":[29,46],"critical":[31,76],"thread":[32,58,77],"at":[33],"maximum":[34],"frequency":[35,40],"while":[36],"scaling":[37],"down":[38],"voltage":[42],"cores":[45],"noncritical":[47],"threads.":[48],"In":[49],"this":[50],"article,":[51],"we":[52,111],"insightful":[55],"breakdown":[56,90],"on":[60,117,132],"a":[61,88,105,113,129],"simulated":[62],"multi-core":[63],"microprocessor.":[64],"balancing":[66,155],"improves":[67],"overall":[68],"giving":[71],"higher":[72],"priority":[73],"to":[74,148],"issue":[80],"queue":[81],"SMT":[84,119],"core.":[85],"detailed":[89,130],"results":[93],"for":[94],"thread-balancing,":[95],"identifying":[96],"benefits":[98],"limitations.":[100],"For":[101],"those":[102],"benchmarks":[103],"where":[104],"benefit":[107],"is":[108],"not":[109],"possible,":[110],"introduce":[112],"novel":[114],"thread-balancing":[115],"mechanism":[116],"can":[122,142,156,162],"consumption.":[125],"have":[127],"performed":[128],"study":[131],"Intel":[134],"microprocessor":[135],"simulator":[136],"parallel":[138],"applications.":[139],"4%":[147],"44%":[149],"with":[150],"negligible":[151],"loss.":[153],"20%":[160],"23%.":[167]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}