{"id":"https://openalex.org/W1990170167","doi":"https://doi.org/10.1145/1837274.1837343","title":"Speedpath analysis under parametric timing models","display_name":"Speedpath analysis under parametric timing models","publication_year":2010,"publication_date":"2010-06-13","ids":{"openalex":"https://openalex.org/W1990170167","doi":"https://doi.org/10.1145/1837274.1837343","mag":"1990170167"},"language":"en","primary_location":{"id":"doi:10.1145/1837274.1837343","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1837274.1837343","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 47th Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074463063","display_name":"Lu\u00eds Guerra e Silva","orcid":"https://orcid.org/0000-0001-5761-0131"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Luis Guerra e Silva","raw_affiliation_strings":["INESC-ID, IST / TU Lisbon, Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID, IST / TU Lisbon, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060124540","display_name":"Joel Phillips","orcid":"https://orcid.org/0000-0002-3437-425X"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel R. Phillips","raw_affiliation_strings":["Cadence Design Systems, Berkeley, CA","Cadence Research Labs, Cadence Design Systems, Berkeley, CA 94704"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Berkeley, CA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Research Labs, Cadence Design Systems, Berkeley, CA 94704","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052100713","display_name":"L. Miguel Silveira","orcid":"https://orcid.org/0000-0003-3542-229X"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["PT","US"],"is_corresponding":false,"raw_author_name":"L. Miguel Silveira","raw_affiliation_strings":["Cadence Res. Labs/INESC-ID, IST / TU Lisbon, Lisbon, Portugal","Cadence Res. Labs / INESC-ID, IST / TU Lisbon, Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Res. Labs/INESC-ID, IST / TU Lisbon, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Res. Labs / INESC-ID, IST / TU Lisbon, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"268","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7127323150634766},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.712174117565155},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6613467931747437},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.6007431745529175},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5678128004074097},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5604513883590698},{"id":"https://openalex.org/keywords/parametric-model","display_name":"Parametric model","score":0.4305298328399658},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.429563045501709},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.42030957341194153},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35896992683410645},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3379838764667511},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24392232298851013},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.20869264006614685},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15423476696014404},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13653123378753662},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12616854906082153},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1090317964553833}],"concepts":[{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7127323150634766},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.712174117565155},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6613467931747437},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.6007431745529175},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5678128004074097},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5604513883590698},{"id":"https://openalex.org/C24574437","wikidata":"https://www.wikidata.org/wiki/Q7135228","display_name":"Parametric model","level":3,"score":0.4305298328399658},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.429563045501709},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.42030957341194153},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35896992683410645},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3379838764667511},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24392232298851013},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.20869264006614685},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15423476696014404},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13653123378753662},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12616854906082153},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1090317964553833},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1837274.1837343","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1837274.1837343","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 47th Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5899999737739563,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1977601065","https://openalex.org/W1979183030","https://openalex.org/W2121845874","https://openalex.org/W2148507902","https://openalex.org/W2163262735","https://openalex.org/W2167480374","https://openalex.org/W2171383332","https://openalex.org/W2171474236","https://openalex.org/W2296319761","https://openalex.org/W2544718775","https://openalex.org/W3144669234"],"related_works":["https://openalex.org/W2130189791","https://openalex.org/W3114476551","https://openalex.org/W2698469377","https://openalex.org/W4388667102","https://openalex.org/W2080035745","https://openalex.org/W4320915609","https://openalex.org/W2016076352","https://openalex.org/W2133361634","https://openalex.org/W2071152039","https://openalex.org/W2163188764"],"abstract_inverted_index":{"The":[0],"clock":[1],"frequency":[2],"of":[3,52,55,74,84,92],"a":[4,56,72,93],"digital":[5],"IC":[6,24],"is":[7],"limited":[8],"by":[9,14,30],"its":[10],"slowest":[11],"paths,":[12,85],"designated":[13],"speedpaths.":[15],"Given":[16],"the":[17,78,90],"extreme":[18],"complexity":[19],"involved":[20],"in":[21],"modeling":[22],"modern":[23],"technologies,":[25],"often":[26],"speedpath":[27],"predictions":[28],"provided":[29],"timing":[31,105],"analysis":[32],"tools":[33],"are":[34],"not":[35],"correct.":[36],"Therefore,":[37],"several":[38],"practical":[39],"techniques":[40,75],"have":[41],"recently":[42],"been":[43],"proposed":[44],"for":[45],"design":[46],"debugging,":[47],"that":[48,76],"combine":[49],"silicon":[50],"stepping":[51],"improved":[53],"versions":[54],"circuit":[57,95],"with":[58],"subsequent":[59],"correlation":[60],"between":[61],"measured":[62],"and":[63],"predicted":[64],"data.":[65],"Addressing":[66],"these":[67],"issues,":[68],"this":[69],"paper":[70],"proposes":[71],"set":[73],"enable":[77],"designer":[79],"to":[80,87,108],"obtain":[81],"reduced":[82],"subsets":[83,99],"guaranteed":[86],"contain":[88],"all":[89],"speedpaths":[91],"given":[94],"or":[96,110],"block.":[97],"Such":[98],"can":[100],"be":[101],"computed":[102],"either":[103],"from":[104,115],"models,":[106],"prior":[107],"fabrication,":[109],"incorporating":[111],"actual":[112],"delay":[113],"measurements":[114],"fabricated":[116],"instances.":[117]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}