{"id":"https://openalex.org/W1992180455","doi":"https://doi.org/10.1145/1837274.1837309","title":"Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms","display_name":"Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms","publication_year":2010,"publication_date":"2010-06-13","ids":{"openalex":"https://openalex.org/W1992180455","doi":"https://doi.org/10.1145/1837274.1837309","mag":"1992180455"},"language":"en","primary_location":{"id":"doi:10.1145/1837274.1837309","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1837274.1837309","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 47th Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035737082","display_name":"Chenjie Yu","orcid":"https://orcid.org/0000-0002-6734-6247"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chenjie Yu","raw_affiliation_strings":["University of Maryland, College Park"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055465444","display_name":"\u041f. \u041f. \u041f\u0435\u0442\u0440\u043e\u0432","orcid":"https://orcid.org/0000-0001-5551-4963"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter Petrov","raw_affiliation_strings":["University of Maryland, College Park"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.5423,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.92983271,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"132","last_page":"137"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7923080921173096},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.6644541621208191},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5909823179244995},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.531622588634491},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5239524841308594},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5066119432449341},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46830928325653076},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4624953269958496},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.45370879769325256},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43404263257980347},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43110886216163635},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09805896878242493}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7923080921173096},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.6644541621208191},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5909823179244995},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.531622588634491},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5239524841308594},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5066119432449341},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46830928325653076},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4624953269958496},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.45370879769325256},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43404263257980347},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43110886216163635},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09805896878242493},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1837274.1837309","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1837274.1837309","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 47th Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.475.847","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.475.847","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cadal.cse.nsysu.edu.tw/seminar/seminar_file/2010/100705_ghlai_paper.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1980419087","https://openalex.org/W1981756989","https://openalex.org/W2014809728","https://openalex.org/W2044206819","https://openalex.org/W2100913437","https://openalex.org/W2101308451","https://openalex.org/W2118703320","https://openalex.org/W2129816520","https://openalex.org/W2141103990","https://openalex.org/W2143773524","https://openalex.org/W2146561901","https://openalex.org/W2152061572","https://openalex.org/W2160609361","https://openalex.org/W2170806963","https://openalex.org/W2545380179","https://openalex.org/W2997147979","https://openalex.org/W4243030509"],"related_works":["https://openalex.org/W2128523353","https://openalex.org/W2152099439","https://openalex.org/W1984163603","https://openalex.org/W2291648581","https://openalex.org/W3130422087","https://openalex.org/W2107644726","https://openalex.org/W2406856881","https://openalex.org/W2011868109","https://openalex.org/W2031026393","https://openalex.org/W2063611263"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,59,88],"methodology":[3],"for":[4,73,81],"off-chip":[5,40,98],"memory":[6,30,41,44,76],"bandwidth":[7,42],"minimization":[8],"through":[9],"application-driven":[10],"L2":[11],"cache":[12],"partitioning":[13],"in":[14],"multi-core":[15,21,60],"systems.":[16],"A":[17],"major":[18],"challenge":[19],"with":[20],"system":[22,61],"design":[23],"is":[24],"the":[25,29,34,38,50,63,96],"widening":[26],"gap":[27],"between":[28],"demand":[31],"generated":[32],"by":[33],"processor":[35],"cores":[36,53,92],"and":[37,43,62,70,93],"limited":[39],"service":[45],"speed.":[46],"This":[47],"severely":[48],"restricts":[49],"number":[51,90],"of":[52,84,91],"that":[54,65],"can":[55,66],"be":[56,67],"integrated":[57],"into":[58],"parallelism":[64],"actually":[68],"achieved":[69],"efficiently":[71],"exploited":[72],"not":[74],"only":[75],"demanding":[77],"applications,":[78],"but":[79],"also":[80],"workloads":[82],"consisting":[83],"many":[85],"tasks":[86],"utilizing":[87],"large":[89],"thus":[94],"exceeding":[95],"available":[97],"bandwidth.":[99]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":6}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
