{"id":"https://openalex.org/W2066278595","doi":"https://doi.org/10.1145/1835420.1835426","title":"Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness","display_name":"Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W2066278595","doi":"https://doi.org/10.1145/1835420.1835426","mag":"2066278595"},"language":"en","primary_location":{"id":"doi:10.1145/1835420.1835426","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1835420.1835426","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040714763","display_name":"Renshen Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Renshen Wang","raw_affiliation_strings":["University of California, San Diego, La Jolla, CA"],"affiliations":[{"raw_affiliation_string":"University of California, San Diego, La Jolla, CA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Evangeline Young","raw_affiliation_strings":["The Chinese University of Hong Kong, Shatin N.T. Hong Kong","The Chinese University of Hong Kong, Shatin, N. T. Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin N.T. Hong Kong","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, N. T. Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039615312","display_name":"Chung\u2010Kuan Cheng","orcid":"https://orcid.org/0000-0002-9865-8390"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chung-Kuan Cheng","raw_affiliation_strings":["University of California, San Diego, La Jolla, CA"],"affiliations":[{"raw_affiliation_string":"University of California, San Diego, La Jolla, CA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5040714763"],"corresponding_institution_ids":["https://openalex.org/I36258959"],"apc_list":null,"apc_paid":null,"fwci":1.4902,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.83479027,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"15","issue":"4","first_page":"1","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9450205564498901},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7804859280586243},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6197414398193359},{"id":"https://openalex.org/keywords/computational-complexity-theory","display_name":"Computational complexity theory","score":0.5796090960502625},{"id":"https://openalex.org/keywords/circuit-complexity","display_name":"Circuit complexity","score":0.5478321313858032},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5194206237792969},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5048085451126099},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.49253591895103455},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.48425838351249695},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4816971719264984},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4448709189891815},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.43087849020957947},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4255774915218353},{"id":"https://openalex.org/keywords/dimension","display_name":"Dimension (graph theory)","score":0.4180067777633667},{"id":"https://openalex.org/keywords/dual-graph","display_name":"Dual graph","score":0.4133569002151489},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3699870705604553},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3526359796524048},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.34244826436042786},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29257142543792725},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13995179533958435},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13512104749679565},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12321770191192627},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.08656445145606995}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9450205564498901},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7804859280586243},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6197414398193359},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.5796090960502625},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.5478321313858032},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5194206237792969},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5048085451126099},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.49253591895103455},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.48425838351249695},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4816971719264984},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4448709189891815},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.43087849020957947},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4255774915218353},{"id":"https://openalex.org/C33676613","wikidata":"https://www.wikidata.org/wiki/Q13415176","display_name":"Dimension (graph theory)","level":2,"score":0.4180067777633667},{"id":"https://openalex.org/C169827030","wikidata":"https://www.wikidata.org/wiki/Q2294516","display_name":"Dual graph","level":4,"score":0.4133569002151489},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3699870705604553},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3526359796524048},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.34244826436042786},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29257142543792725},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13995179533958435},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13512104749679565},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12321770191192627},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.08656445145606995},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C203776342","wikidata":"https://www.wikidata.org/wiki/Q1378376","display_name":"Line graph","level":3,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1835420.1835426","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1835420.1835426","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.190.6414","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.190.6414","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cse.cuhk.edu.hk/%7Efyyoung/paper/todaes10_3d.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5699999928474426,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1544642978","https://openalex.org/W1964700557","https://openalex.org/W1964716955","https://openalex.org/W1975442866","https://openalex.org/W1981505946","https://openalex.org/W2023112489","https://openalex.org/W2036265926","https://openalex.org/W2062567760","https://openalex.org/W2066577300","https://openalex.org/W2125531773","https://openalex.org/W2129664231","https://openalex.org/W2138401961","https://openalex.org/W2148385942","https://openalex.org/W2168444726","https://openalex.org/W2171825402","https://openalex.org/W4235935333","https://openalex.org/W4255529553"],"related_works":["https://openalex.org/W3010631755","https://openalex.org/W2186482337","https://openalex.org/W2115502122","https://openalex.org/W2783276420","https://openalex.org/W2903073708","https://openalex.org/W2781601456","https://openalex.org/W2138401961","https://openalex.org/W4249576260","https://openalex.org/W4388721364","https://openalex.org/W2167104477"],"abstract_inverted_index":{"Interconnect":[0],"dominated":[1],"electronic":[2],"design":[3,36,130],"stimulates":[4],"a":[5,32,63],"demand":[6],"for":[7,128],"developing":[8],"circuits":[9],"on":[10,53],"the":[11,45,54,67,75,79,88,101,111,126],"third":[12],"dimension,":[13],"leading":[14],"to":[15,51],"3-D":[16,25,40,52,76,105,134],"integration.":[17],"Recent":[18],"advances":[19],"in":[20,38,91,104,110,125],"chip":[21],"fabrication":[22],"technology":[23],"enable":[24],"circuit":[26],"manufacturing.":[27],"However,":[28],"there":[29],"is":[30,108],"still":[31],"possible":[33,123],"barrier":[34],"of":[35,47,56,66,93,133],"complexity":[37,103],"exploiting":[39],"technologies.":[41],"This":[42],"article":[43],"discusses":[44],"impact":[46],"migrating":[48],"from":[49],"2-D":[50,89],"difficulty":[55],"floorplanning":[57],"and":[58,78,117,131],"placement.":[59],"By":[60,96],"looking":[61],"at":[62],"basic":[64],"formulation":[65],"graph":[68],"cuboidal":[69],"dual":[70],"problem,":[71],"we":[72],"show":[73,122],"that":[74],"cases":[77,82,90],"3-layer":[80],"2.5-D":[81],"are":[83],"fundamentally":[84],"more":[85],"difficult":[86],"than":[87],"terms":[92],"computational":[94],"complexity.":[95],"comparison":[97],"among":[98],"these":[99],"cases,":[100],"intrinsic":[102],"floorplan":[106],"structures":[107],"revealed":[109],"hard-to-decide":[112],"relations":[113],"between":[114],"topological":[115],"connections":[116],"geometrical":[118],"contacts.":[119],"The":[120],"results":[121],"challenges":[124],"future":[127],"physical":[129],"CAD":[132],"integrated":[135],"circuits.":[136]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}