{"id":"https://openalex.org/W2007929622","doi":"https://doi.org/10.1145/1815961.1815972","title":"The virtual write queue","display_name":"The virtual write queue","publication_year":2010,"publication_date":"2010-06-19","ids":{"openalex":"https://openalex.org/W2007929622","doi":"https://doi.org/10.1145/1815961.1815972","mag":"2007929622"},"language":"en","primary_location":{"id":"doi:10.1145/1815961.1815972","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1815961.1815972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 37th annual international symposium on Computer architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014845043","display_name":"Jeffrey Stuecheli","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jeffrey Stuecheli","raw_affiliation_strings":["The University of Texas, &amp; IBM Corp., Austin, TX, USA","The University of Texas, & IBM Corp., Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"The University of Texas, &amp; IBM Corp., Austin, TX, USA","institution_ids":[]},{"raw_affiliation_string":"The University of Texas, & IBM Corp., Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091141326","display_name":"Dimitris Kaseridis","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dimitris Kaseridis","raw_affiliation_strings":["The University of Texas, Austin, TX, USA",", The University of Texas, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":", The University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057908129","display_name":"David Daly","orcid":"https://orcid.org/0000-0001-9678-3721"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Daly","raw_affiliation_strings":["IBM, Yorktown Heights, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM, Yorktown Heights, NY, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030648912","display_name":"Hillery C. Hunter","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hillery C. Hunter","raw_affiliation_strings":["IBM, Yorktown Heights, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM, Yorktown Heights, NY, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068885069","display_name":"Lizy K. John","orcid":"https://orcid.org/0000-0002-8747-5214"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lizy K. John","raw_affiliation_strings":["The University of Texas, Austin, TX, USA",", The University of Texas, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":", The University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5014845043"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":7.328,"has_fulltext":false,"cited_by_count":109,"citation_normalized_percentile":{"value":0.97423495,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"72","last_page":"82"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8766756057739258},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7252567410469055},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.7097345590591431},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.648863673210144},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6336163878440857},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5539481043815613},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.505842924118042},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4969780743122101},{"id":"https://openalex.org/keywords/virtual-memory","display_name":"Virtual memory","score":0.4966657757759094},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.4790140986442566},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4718342423439026},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45619824528694153},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4513702094554901},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44802671670913696},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.44173675775527954},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4377681016921997},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.43096688389778137},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.41453057527542114},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.41298553347587585},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3995002508163452},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.3839358687400818},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.24027463793754578}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8766756057739258},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7252567410469055},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.7097345590591431},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.648863673210144},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6336163878440857},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5539481043815613},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.505842924118042},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4969780743122101},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.4966657757759094},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.4790140986442566},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4718342423439026},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45619824528694153},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4513702094554901},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44802671670913696},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.44173675775527954},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4377681016921997},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.43096688389778137},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.41453057527542114},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.41298553347587585},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3995002508163452},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.3839358687400818},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.24027463793754578},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1815961.1815972","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1815961.1815972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 37th annual international symposium on Computer architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W1602774826","https://openalex.org/W1975223858","https://openalex.org/W1975987522","https://openalex.org/W2048588974","https://openalex.org/W2100108901","https://openalex.org/W2102871765","https://openalex.org/W2111397647","https://openalex.org/W2114726466","https://openalex.org/W2115172404","https://openalex.org/W2115401821","https://openalex.org/W2119033207","https://openalex.org/W2148954445","https://openalex.org/W2164264749","https://openalex.org/W2167233984","https://openalex.org/W2168582504","https://openalex.org/W2275803065","https://openalex.org/W6631059261"],"related_works":["https://openalex.org/W3108993429","https://openalex.org/W2587873888","https://openalex.org/W2782503170","https://openalex.org/W2047684617","https://openalex.org/W4317815260","https://openalex.org/W1982632559","https://openalex.org/W4321458411","https://openalex.org/W4382407528","https://openalex.org/W2041174925","https://openalex.org/W4233816696"],"abstract_inverted_index":{"In":[0,36],"computer":[1],"architecture,":[2],"caches":[3],"have":[4,20],"primarily":[5],"been":[6],"viewed":[7],"as":[8,100],"a":[9,55,75],"means":[10],"to":[11,32],"hide":[12],"memory":[13,51,64,70,83,125,141,182],"latency":[14,137],"from":[15],"the":[16,24,33,42,67,82,122,159,185],"CPU.":[17],"Cache":[18],"policies":[19],"focused":[21],"on":[22,130,171],"anticipating":[23],"CPU's":[25],"data":[26],"needs,":[27],"and":[28,53,127,134,144],"are":[29],"mostly":[30],"oblivious":[31],"main":[34,50,63,124],"memory.":[35],"this":[37,103],"paper,":[38],"we":[39,73,156],"demonstrate":[40,157],"that":[41,106,118,158],"era":[43],"of":[44,59,86,96,110,121,153,179],"many-core":[45],"architectures":[46,112],"has":[47],"created":[48],"new":[49,56],"bottlenecks,":[52],"mandates":[54],"approach:":[57],"coordination":[58],"cache":[60,68],"policy":[61],"with":[62,175],"characteristics.":[65],"Using":[66],"for":[69],"optimization":[71],"purposes,":[72],"propose":[74],"Virtual":[76,161],"Write":[77,162],"Queue":[78,163],"which":[79],"dramatically":[80],"expands":[81],"controller's":[84],"visibility":[85],"processor":[87],"behavior,":[88],"at":[89],"low":[90],"implementation":[91],"overhead.":[92],"Through":[93,149],"memory-centric":[94],"modification":[95],"existing":[97],"policies,":[98],"such":[99],"scheduled":[101],"writebacks,":[102],"paper":[104],"demonstrates":[105],"performance":[107,147],"limiting":[108],"effects":[109],"highly-threaded":[111],"can":[113,138],"be":[114,139],"overcome.":[115],"We":[116],"show":[117],"through":[119],"awareness":[120],"physical":[123],"layout":[126],"by":[128],"focusing":[129],"writes,":[131],"both":[132],"read":[133],"write":[135],"average":[136,166],"shortened,":[140],"power":[142,183],"reduced,":[143],"overall":[145,177],"system":[146],"improved.":[148],"full-system":[150],"cycle-accurate":[151],"simulations":[152],"SPEC":[154],"cpu2006,":[155],"proposed":[160],"achieves":[164],"an":[165,176],"10.9%":[167],"system-level":[168],"throughput":[169],"improvement":[170],"memory-intensive":[172],"workloads,":[173],"along":[174],"reduction":[178],"8.7%":[180],"in":[181],"across":[184],"whole":[186],"suite.":[187]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":7},{"year":2019,"cited_by_count":13},{"year":2018,"cited_by_count":15},{"year":2017,"cited_by_count":8},{"year":2016,"cited_by_count":8},{"year":2015,"cited_by_count":9},{"year":2014,"cited_by_count":16},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":13}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
