{"id":"https://openalex.org/W2164515066","doi":"https://doi.org/10.1145/1811100.1811107","title":"Process-induced skew variation for scaled 2-D and 3-D ICs","display_name":"Process-induced skew variation for scaled 2-D and 3-D ICs","publication_year":2010,"publication_date":"2010-06-13","ids":{"openalex":"https://openalex.org/W2164515066","doi":"https://doi.org/10.1145/1811100.1811107","mag":"2164515066"},"language":"en","primary_location":{"id":"doi:10.1145/1811100.1811107","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1811100.1811107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/150051","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100385218","display_name":"Xu Hu","orcid":"https://orcid.org/0000-0002-4030-4899"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Hu Xu","raw_affiliation_strings":["LSI-EPFL, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LSI-EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031542707","display_name":"Vasilis F. Pavlidis","orcid":"https://orcid.org/0000-0002-4063-4652"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Vasilis F. Pavlidis","raw_affiliation_strings":["LSI-EPFL, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LSI-EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["LSI-EPFL, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LSI-EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"17","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.8635025024414062},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7775935530662537},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.7058333158493042},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.6651384830474854},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5792537331581116},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.5137706995010376},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4824941158294678},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.45439887046813965},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4453691244125366},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4377305507659912},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3902572989463806},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.386458158493042},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.357108473777771},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3151676058769226},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.23869383335113525},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20339801907539368},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20337653160095215},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1752154529094696},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.14401182532310486},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10140925645828247},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.08379915356636047},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07160398364067078}],"concepts":[{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.8635025024414062},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7775935530662537},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.7058333158493042},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.6651384830474854},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5792537331581116},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5137706995010376},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4824941158294678},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.45439887046813965},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4453691244125366},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4377305507659912},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3902572989463806},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.386458158493042},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.357108473777771},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3151676058769226},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.23869383335113525},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20339801907539368},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20337653160095215},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1752154529094696},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.14401182532310486},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10140925645828247},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.08379915356636047},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07160398364067078},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1145/1811100.1811107","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1811100.1811107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:150051","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/150051","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/e2e1ad04-7ea6-46c2-8a6e-4e313737b225","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/e2e1ad04-7ea6-46c2-8a6e-4e313737b225","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Xu, H, Pavlidis, V F & De Micheli, G 2010, Process-induced skew variation for scaled 2-D and 3-D ICs. in International Workshop on System Level Interconnect Prediction, SLIP|Int. Workshop Syst. Level Interconnect Predict. SLIP. Proceedings of the System Level Interconnect Prediction Workshop, pp. 17-24, 12th ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP'10, Anaheim, CA, 1/07/10. https://doi.org/10.1145/1811100.1811107","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/e2e1ad04-7ea6-46c2-8a6e-4e313737b225","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/processinduced-skew-variation-for-scaled-2d-and-3d-ics(e2e1ad04-7ea6-46c2-8a6e-4e313737b225).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Xu, H, Pavlidis, V F & De Micheli, G 2010, Process-induced skew variation for scaled 2-D and 3-D ICs. in International Workshop on System Level Interconnect Prediction, SLIP|Int. Workshop Syst. Level Interconnect Predict. SLIP. Proceedings of the System Level Interconnect Prediction Workshop, pp. 17-24, 12th ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP'10, Anaheim, CA, 1/07/10. https://doi.org/10.1145/1811100.1811107","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:150051","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/150051","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320320924","display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","ror":"https://ror.org/00yjd3n13"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W73765150","https://openalex.org/W1528914157","https://openalex.org/W1538573330","https://openalex.org/W1572287951","https://openalex.org/W1984588379","https://openalex.org/W2033443176","https://openalex.org/W2045967129","https://openalex.org/W2070451661","https://openalex.org/W2097006642","https://openalex.org/W2105982376","https://openalex.org/W2106565868","https://openalex.org/W2115246441","https://openalex.org/W2115708507","https://openalex.org/W2116021798","https://openalex.org/W2116296320","https://openalex.org/W2120116751","https://openalex.org/W2125669810","https://openalex.org/W2129785295","https://openalex.org/W2130601386","https://openalex.org/W2137807823","https://openalex.org/W2147890024","https://openalex.org/W2148292324","https://openalex.org/W2155707315","https://openalex.org/W2158130267","https://openalex.org/W2169009507","https://openalex.org/W3148768868","https://openalex.org/W4238724481","https://openalex.org/W4294881123","https://openalex.org/W6634220963","https://openalex.org/W6662008051"],"related_works":["https://openalex.org/W2164834710","https://openalex.org/W4232019485","https://openalex.org/W2028052815","https://openalex.org/W4327499872","https://openalex.org/W2123512677","https://openalex.org/W2163318442","https://openalex.org/W2116259070","https://openalex.org/W2128528443","https://openalex.org/W2066822161","https://openalex.org/W2132548233"],"abstract_inverted_index":{"Technology":[0],"scaling":[1,122,178],"and":[2,40,146,159,181],"three-dimensional":[3],"integration":[4,219],"are":[5,150],"two":[6,135],"design":[7,18,74,136],"paradigms":[8,19,137],"that":[9,141],"offer":[10],"high":[11,160],"device":[12],"density.":[13],"Process":[14],"variations":[15,27,69],"affect":[16],"these":[17,73,134],"in":[20,53,112,171,182],"different":[21,129],"ways.":[22],"The":[23,78,97],"effect":[24,63],"of":[25,49,64,68,72,80,99,148,190,233],"process":[26],"on":[28,70],"clock":[29,94,116,156,166,194,200],"skew":[30,83,103,117,157,228],"for":[31,41,87],"a":[32,42,127,154,172,183,213],"2-D":[33],"circuit":[34,44,175,185],"implemented":[35],"at":[36,212],"scaled":[37,89],"technology":[38,121,144,177,216,235],"nodes":[39],"3-D":[43,184,218],"with":[45,186],"an":[46,187,224],"increasing":[47,188],"number":[48,147,189],"planes":[50,149],"is":[51,76,85,105,138,169,179,220],"investigated":[52],"this":[54,113,193],"paper.":[55],"An":[56],"accurate":[57],"model":[58,104],"used":[59],"to":[60,120,152,206,222,226],"describe":[61],"the":[62,65,81,100,115,142,197,231],"proper":[66,210],"sources":[67],"each":[71],"approaches":[75],"proposed.":[77],"distribution":[79,95],"pair-wise":[82],"variation":[84,118,158,229],"obtained":[86],"single":[88],"or":[90],"multi-plane":[91],"(not":[92],"scaled)":[93],"networks.":[96],"accuracy":[98],"presented":[101],"statistical":[102],"verified":[106],"through":[107],"Monte-Carlo":[108],"simulations.":[109],"As":[110],"shown":[111,221],"paper,":[114],"due":[119],"and/or":[123],"die":[124],"stacking":[125],"exhibits":[126],"considerably":[128],"behavior.":[130],"A":[131,163],"comparison":[132],"between":[133],"offered":[139],"such":[140],"appropriate":[143],"node":[145],"selected":[151],"produce":[153],"low":[155],"operating":[161],"frequency.":[162],"popular":[164],"global":[165],"tree":[167,195],"topology":[168],"employed":[170],"planar":[173],"(2-D)":[174],"where":[176],"applied":[180],"planes.":[191],"For":[192],"topology,":[196],"maximum":[198],"supported":[199],"frequency":[201],"increases":[202],"from":[203],"2.75":[204],"GHz":[205,208],"3.74":[207],"by":[209],"die-stacking":[211],"90":[214],"nm":[215],"node.":[217],"be":[223],"alternative":[225],"reduce":[227],"without":[230],"need":[232],"aggressive":[234],"scaling.":[236]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}