{"id":"https://openalex.org/W1976166844","doi":"https://doi.org/10.1145/1810085.1810109","title":"Enigma","display_name":"Enigma","publication_year":2010,"publication_date":"2010-06-02","ids":{"openalex":"https://openalex.org/W1976166844","doi":"https://doi.org/10.1145/1810085.1810109","mag":"1976166844"},"language":"en","primary_location":{"id":"doi:10.1145/1810085.1810109","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1810085.1810109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th ACM International Conference on Supercomputing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008977627","display_name":"Lixin Zhang","orcid":"https://orcid.org/0000-0001-6799-3586"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Lixin Zhang","raw_affiliation_strings":["IBM Research, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Research, Austin, TX","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073521684","display_name":"Evan W. Speight","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Evan Speight","raw_affiliation_strings":["IBM Research, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Research, Austin, TX","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113994263","display_name":"Ram Rajamony","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram Rajamony","raw_affiliation_strings":["IBM Research, Austin, TX"],"affiliations":[{"raw_affiliation_string":"IBM Research, Austin, TX","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101903806","display_name":"Lin Jiang","orcid":"https://orcid.org/0000-0001-5876-5047"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Lin","raw_affiliation_strings":["Intel Corp., Hillsboro, OR","Intel Corporation, Hillsboro, OR#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5008977627"],"corresponding_institution_ids":["https://openalex.org/I4210156936"],"apc_list":null,"apc_paid":null,"fwci":1.4981,"has_fulltext":false,"cited_by_count":38,"citation_normalized_percentile":{"value":0.8284668,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8499701023101807},{"id":"https://openalex.org/keywords/logical-address","display_name":"Logical address","score":0.8365172743797302},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.7668189406394958},{"id":"https://openalex.org/keywords/translation-lookaside-buffer","display_name":"Translation lookaside buffer","score":0.6894950866699219},{"id":"https://openalex.org/keywords/address-space","display_name":"Address space","score":0.6678069829940796},{"id":"https://openalex.org/keywords/virtual-memory","display_name":"Virtual memory","score":0.5910680294036865},{"id":"https://openalex.org/keywords/address-bus","display_name":"Address bus","score":0.5745705366134644},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5632845759391785},{"id":"https://openalex.org/keywords/translation","display_name":"Translation (biology)","score":0.46791937947273254},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4398166537284851},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.4268485903739929},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3632204234600067},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3160838782787323},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.25925326347351074},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.25189006328582764},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.22565549612045288},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.10062184929847717}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8499701023101807},{"id":"https://openalex.org/C186799414","wikidata":"https://www.wikidata.org/wiki/Q3494571","display_name":"Logical address","level":4,"score":0.8365172743797302},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.7668189406394958},{"id":"https://openalex.org/C116007543","wikidata":"https://www.wikidata.org/wiki/Q1071403","display_name":"Translation lookaside buffer","level":4,"score":0.6894950866699219},{"id":"https://openalex.org/C144240696","wikidata":"https://www.wikidata.org/wiki/Q367204","display_name":"Address space","level":2,"score":0.6678069829940796},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.5910680294036865},{"id":"https://openalex.org/C54714250","wikidata":"https://www.wikidata.org/wiki/Q178048","display_name":"Address bus","level":3,"score":0.5745705366134644},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5632845759391785},{"id":"https://openalex.org/C149364088","wikidata":"https://www.wikidata.org/wiki/Q185917","display_name":"Translation (biology)","level":4,"score":0.46791937947273254},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4398166537284851},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.4268485903739929},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3632204234600067},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3160838782787323},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.25925326347351074},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.25189006328582764},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.22565549612045288},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.10062184929847717},{"id":"https://openalex.org/C105580179","wikidata":"https://www.wikidata.org/wiki/Q188928","display_name":"Messenger RNA","level":3,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1810085.1810109","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1810085.1810109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th ACM International Conference on Supercomputing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W127139334","https://openalex.org/W1552694545","https://openalex.org/W1555915743","https://openalex.org/W1974232202","https://openalex.org/W1990260376","https://openalex.org/W1990975467","https://openalex.org/W2005961863","https://openalex.org/W2033508089","https://openalex.org/W2059743873","https://openalex.org/W2097773861","https://openalex.org/W2101668240","https://openalex.org/W2105332698","https://openalex.org/W2109978596","https://openalex.org/W2112300321","https://openalex.org/W2114875708","https://openalex.org/W2116578804","https://openalex.org/W2119502203","https://openalex.org/W2130787286","https://openalex.org/W2133806301","https://openalex.org/W2138360141","https://openalex.org/W2156003674","https://openalex.org/W2158924248","https://openalex.org/W2169387148","https://openalex.org/W2169395663","https://openalex.org/W2293221651","https://openalex.org/W2505437262","https://openalex.org/W2725179571","https://openalex.org/W2751601659","https://openalex.org/W3152703111","https://openalex.org/W4301657354","https://openalex.org/W6605219577","https://openalex.org/W6744131798"],"related_works":["https://openalex.org/W743995","https://openalex.org/W2381395788","https://openalex.org/W1976166844","https://openalex.org/W4293160630","https://openalex.org/W2501386197","https://openalex.org/W2349388084","https://openalex.org/W2987168062","https://openalex.org/W2383233881","https://openalex.org/W2121519027","https://openalex.org/W4233273983"],"abstract_inverted_index":{"Most":[0],"modern":[1],"microprocessors":[2],"provide":[3],"hardware":[4],"support":[5],"for":[6],"rapidly":[7],"translating":[8],"a":[9,14,45,83,94,147,186],"program":[10],"logical":[11,90],"address":[12,17,49,60,73,91,97,192],"to":[13,48,86,93,146,173,185],"system":[15,107,175],"physical":[16,68],"(PA).":[18],"Translation":[19],"typically":[20],"sits":[21],"on":[22,179],"the":[23,53,56,72,89,105,119,154,159,174,189],"critical":[24],"path":[25],"of":[26,55,191],"every":[27],"memory":[28,162],"access,":[29],"since":[30],"an":[31,144],"access":[32],"cannot":[33],"usually":[34],"be":[35,65,166,183],"performed":[36],"until":[37,62],"after":[38],"it":[39,197],"has":[40],"been":[41],"translated.":[42],"Enigma":[43,70,142],"is":[44,111,137],"novel":[46],"approach":[47],"translation":[50,61,74,170,193],"that":[51,76,181],"defers":[52],"bulk":[54,190],"work":[57,194],"associated":[58],"with":[59,82],"data":[63],"must":[64,165,182],"retrieved":[66],"from":[67,88,198],"memory.":[69],"replaces":[71],"unit":[75,85,171],"exists":[77],"in":[78,123,153,203],"each":[79,199],"conventional":[80],"core":[81,202],"simpler":[84],"translate":[87],"space":[92],"new":[95],"intermediate":[96],"(IA)":[98],"space.":[99],"Intermediate":[100],"addresses":[101],"are":[102],"unique":[103],"across":[104],"entire":[106,155],"except":[108],"where":[109],"sharing":[110],"required":[112],"or":[113,163],"desired,":[114],"and":[115,134,161,195],"their":[116],"use":[117],"sidesteps":[118],"\"synonym\"":[120],"problem":[121],"present":[122],"logically":[124],"tagged":[125],"caches.":[126],"All":[127],"cache":[128,152],"addressing,":[129],"as":[130,132],"well":[131],"I/O":[133,164],"coherence":[135],"traffic,":[136],"carried":[138],"out":[139],"using":[140],"IA.":[141],"translates":[143],"IA":[145,180],"PA":[148],"only":[149],"when":[150],"no":[151],"CMP":[156],"can":[157],"satisfy":[158],"request":[160],"accessed.":[167],"A":[168],"central":[169],"attached":[172],"bus":[176],"performs":[177],"translations":[178],"resolved":[184],"PA.":[187],"Deferring":[188],"removing":[196],"individual":[200],"processor":[201],"this":[204],"manner":[205],"affords":[206],"many":[207],"benefits.":[208]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":4},{"year":2013,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
