{"id":"https://openalex.org/W1987883647","doi":"https://doi.org/10.1145/1785481.1785582","title":"Wirelength-driven force-directed 3D FPGA placement","display_name":"Wirelength-driven force-directed 3D FPGA placement","publication_year":2010,"publication_date":"2010-05-16","ids":{"openalex":"https://openalex.org/W1987883647","doi":"https://doi.org/10.1145/1785481.1785582","mag":"1987883647"},"language":"en","primary_location":{"id":"doi:10.1145/1785481.1785582","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785582","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089747779","display_name":"Wentao Sui","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wentao Sui","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110234701","display_name":"Sheqin Dong","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Sheqin Dong","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034755987","display_name":"Jinian Bian","orcid":"https://orcid.org/0000-0002-4322-1503"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinian Bian","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.2942,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61315766,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"435","last_page":"440"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.790372371673584},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.6705178618431091},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6558104157447815},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.6233726143836975},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5959475636482239},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5906941294670105},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5074602961540222},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.47020986676216125},{"id":"https://openalex.org/keywords/dimension","display_name":"Dimension (graph theory)","score":0.4570823013782501},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4549517035484314},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34438446164131165},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2645552158355713},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25910624861717224},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.25457268953323364},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1956060826778412},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.131597101688385}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.790372371673584},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.6705178618431091},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6558104157447815},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.6233726143836975},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5959475636482239},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5906941294670105},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5074602961540222},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.47020986676216125},{"id":"https://openalex.org/C33676613","wikidata":"https://www.wikidata.org/wiki/Q13415176","display_name":"Dimension (graph theory)","level":2,"score":0.4570823013782501},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4549517035484314},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34438446164131165},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2645552158355713},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25910624861717224},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.25457268953323364},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1956060826778412},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.131597101688385},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1785481.1785582","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785582","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","score":0.7900000214576721,"id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W2002041333","https://openalex.org/W2041266765","https://openalex.org/W2079078065","https://openalex.org/W2107398534","https://openalex.org/W2120129706","https://openalex.org/W2139637699","https://openalex.org/W2143034719","https://openalex.org/W2157558963","https://openalex.org/W2164132095","https://openalex.org/W2170034300","https://openalex.org/W2172048239"],"related_works":["https://openalex.org/W2028789485","https://openalex.org/W1968931833","https://openalex.org/W2475407120","https://openalex.org/W4245174233","https://openalex.org/W2122425352","https://openalex.org/W108855261","https://openalex.org/W2098132017","https://openalex.org/W2076431810","https://openalex.org/W4244167835","https://openalex.org/W2031837447"],"abstract_inverted_index":{"In":[0],"this":[1,122],"paper,":[2],"a":[3,74],"wirelength-driven":[4],"force-directed":[5,27],"three-dimension":[6],"(3-D)":[7],"Field":[8],"Programmable":[9],"Gate":[10],"Arrays":[11],"(FPGA)":[12],"placement":[13,120],"algorithm":[14,19,123],"(3D-WFP)":[15],"is":[16,20,79,87,111],"presented.":[17],"The":[18],"composed":[21],"of":[22,70,108],"three":[23],"stages:":[24],"Overlap":[25],"permitted":[26,103],"2-D":[28,49],"placement,":[29,51],"legalization":[30],"and":[31,58,138],"3-D":[32,39,75,118],"layer":[33,44],"partition.":[34],"Different":[35],"from":[36],"traditional":[37],"partition-based":[38],"placers,":[40],"we":[41],"adjust":[42],"the":[43,48,55,62,68,71,91,98,106,109,125,134,140],"partition":[45],"process":[46],"after":[47],"global":[50,56],"which":[52],"effectively":[53],"provides":[54],"interconnection":[57],"timing":[59,142],"information":[60],"for":[61],"next":[63],"two":[64],"sub-steps.":[65],"To":[66],"legalize":[67],"position":[69],"logic":[72],"block,":[73],"space":[76],"filling":[77],"curve":[78],"adopted.":[80],"A":[81],"low":[82],"temperature":[83],"simulated":[84],"annealing":[85],"(SA)":[86],"used":[88],"to":[89,104,115],"determine":[90],"blocks":[92,96],"final":[93],"layer.":[94],"Only":[95],"with":[97],"same":[99,135,141],"horizontal":[100],"coordinate":[101],"are":[102],"interchange,":[105],"speed":[107],"SA":[110],"very":[112],"fast.":[113],"Compared":[114],"recently":[116],"publish":[117],"FPGA":[119],"work,":[121],"improves":[124],"half":[126],"perimeter":[127],"wire-length":[128],"(HPWL)":[129],"by":[130],"8.57%,":[131],"almost":[132],"at":[133],"time":[136],"cost":[137],"keeps":[139],"performance.":[143]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}