{"id":"https://openalex.org/W1964142402","doi":"https://doi.org/10.1145/1785481.1785572","title":"Characteristics of MS-CMOS logic in sub-32nm technologies","display_name":"Characteristics of MS-CMOS logic in sub-32nm technologies","publication_year":2010,"publication_date":"2010-05-16","ids":{"openalex":"https://openalex.org/W1964142402","doi":"https://doi.org/10.1145/1785481.1785572","mag":"1964142402"},"language":"en","primary_location":{"id":"doi:10.1145/1785481.1785572","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785572","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033624519","display_name":"Kagan Irez","orcid":"https://orcid.org/0000-0002-6871-7740"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kagan Irez","raw_affiliation_strings":["Columbia University , New York, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Columbia University , New York, NY, USA","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033329541","display_name":"Jiaping Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiaping Hu","raw_affiliation_strings":["Columbia University , New York, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Columbia University , New York, NY, USA","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000640914","display_name":"C. Zukowski","orcid":null},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles A. Zukowski","raw_affiliation_strings":["Columbia University, New York, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Columbia University, New York, NY, USA","institution_ids":["https://openalex.org/I78577930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78577930"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"393","last_page":"396"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7881178855895996},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.7095323801040649},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6891806125640869},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6827158331871033},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.6352040767669678},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6300160884857178},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6034928560256958},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.600324273109436},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5074703097343445},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.5034160017967224},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.4966633915901184},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.49235522747039795},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.4664705693721771},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.4621826410293579},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44601112604141235},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.44289273023605347},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.4395518898963928},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.40524667501449585},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3620951175689697},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.305478572845459},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15484794974327087}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7881178855895996},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.7095323801040649},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6891806125640869},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6827158331871033},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.6352040767669678},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6300160884857178},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6034928560256958},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.600324273109436},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5074703097343445},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.5034160017967224},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.4966633915901184},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.49235522747039795},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.4664705693721771},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.4621826410293579},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44601112604141235},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.44289273023605347},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.4395518898963928},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.40524667501449585},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3620951175689697},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.305478572845459},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15484794974327087},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1785481.1785572","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785572","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1979587941","https://openalex.org/W1983067779","https://openalex.org/W2000714314","https://openalex.org/W2027385314","https://openalex.org/W2046387718","https://openalex.org/W2046826624","https://openalex.org/W2078855203","https://openalex.org/W2095816730","https://openalex.org/W2106288082","https://openalex.org/W2126700722","https://openalex.org/W2143634842","https://openalex.org/W2145606027","https://openalex.org/W2160215564","https://openalex.org/W2548778905","https://openalex.org/W6681532115"],"related_works":["https://openalex.org/W1513486344","https://openalex.org/W2132134751","https://openalex.org/W2949071089","https://openalex.org/W2042037542","https://openalex.org/W2167556916","https://openalex.org/W3106325237","https://openalex.org/W2184285466","https://openalex.org/W2134806353","https://openalex.org/W2188722559","https://openalex.org/W1964142402"],"abstract_inverted_index":{"This":[0],"paper":[1],"explores":[2],"the":[3,74],"characteristics":[4],"of":[5,31,50,67,90],"Monotonic-Static":[6],"CMOS":[7],"and":[8,33,45,58,95],"its":[9],"potential":[10,86],"applications":[11],"in":[12,16,48,88,98],"gate":[13,24],"leakage":[14,25],"reduction":[15],"a":[17,39,64,100],"hypothetical":[18],"22nm":[19],"Bulk-Si":[20],"technology":[21],"with":[22],"significant":[23],"currents.":[26],"Using":[27],"test":[28],"circuits":[29],"consisting":[30],"NAND":[32],"NOR":[34],"logic":[35,47],"gates,":[36],"we":[37],"performed":[38],"comparison":[40],"among":[41],"static,":[42],"monotonic":[43],"static":[44],"domino":[46],"terms":[49,89],"various":[51],"properties":[52],"including":[53],"power,":[54,92],"delay,":[55],"noise":[56,96],"margin":[57,97],"area.":[59],"Comparisons":[60],"were":[61],"done":[62],"over":[63],"wide":[65],"range":[66],"possible":[68],"transistor":[69],"widths":[70],"to":[71],"fully":[72],"characterize":[73],"tradeoffs":[75],"for":[76],"each":[77],"circuit":[78],"type.":[79],"Experimental":[80],"results":[81],"show":[82],"that":[83],"MS-CMOS":[84],"has":[85],"advantages":[87],"stand-by":[91],"evaluation":[93],"speed":[94],"such":[99],"technology.":[101]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}