{"id":"https://openalex.org/W2041997506","doi":"https://doi.org/10.1145/1785481.1785552","title":"Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs","display_name":"Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs","publication_year":2010,"publication_date":"2010-05-16","ids":{"openalex":"https://openalex.org/W2041997506","doi":"https://doi.org/10.1145/1785481.1785552","mag":"2041997506"},"language":"en","primary_location":{"id":"doi:10.1145/1785481.1785552","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785552","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/148836","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048126449","display_name":"Mohamed M. Sabry","orcid":"https://orcid.org/0000-0001-9498-3818"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Mohamed M. Sabry","raw_affiliation_strings":["EPFL, lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062549550","display_name":"Martino Ruggiero","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Martino Ruggiero","raw_affiliation_strings":["University of Bologna, Bologna, Italy","University of Bologna , Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"University of Bologna , Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050340889","display_name":"Pablo Valle","orcid":"https://orcid.org/0000-0002-0588-316X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pablo G. Del Valle","raw_affiliation_strings":["UCM, Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"UCM, Madrid, Spain","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048126449"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":1.2635,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.80913403,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"305","last_page":"310"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8340615034103394},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6641417741775513},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5897842049598694},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5835887789726257},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5376545190811157},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5363520383834839},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.5115583539009094},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4829501509666443},{"id":"https://openalex.org/keywords/benchmarking","display_name":"Benchmarking","score":0.46742528676986694},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4515003263950348},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.44835788011550903},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.4154103398323059},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4092440903186798},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2411544919013977}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8340615034103394},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6641417741775513},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5897842049598694},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5835887789726257},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5376545190811157},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5363520383834839},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.5115583539009094},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4829501509666443},{"id":"https://openalex.org/C86251818","wikidata":"https://www.wikidata.org/wiki/Q816754","display_name":"Benchmarking","level":2,"score":0.46742528676986694},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4515003263950348},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.44835788011550903},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.4154103398323059},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4092440903186798},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2411544919013977},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1785481.1785552","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785552","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.233.5884","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.233.5884","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://infoscience.epfl.ch/record/148836/files/p305-sabry.pdf?version%3D4","raw_type":"text"},{"id":"pmh:oai:infoscience.epfl.ch:148836","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/148836","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:148836","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/148836","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.75}],"awards":[],"funders":[{"id":"https://openalex.org/F4320338370","display_name":"FP7 Information and Communication Technologies","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W191558368","https://openalex.org/W1559283829","https://openalex.org/W1686420892","https://openalex.org/W2050448441","https://openalex.org/W2056634338","https://openalex.org/W2099708455","https://openalex.org/W2106464290","https://openalex.org/W2112457107","https://openalex.org/W2117324528","https://openalex.org/W2140250706","https://openalex.org/W2147943147","https://openalex.org/W2150938982","https://openalex.org/W2243416539","https://openalex.org/W2911669905","https://openalex.org/W4248800093"],"related_works":["https://openalex.org/W2092181573","https://openalex.org/W2576551918","https://openalex.org/W2056447856","https://openalex.org/W2133489088","https://openalex.org/W2115222420","https://openalex.org/W2126408955","https://openalex.org/W2998838928","https://openalex.org/W2783693002","https://openalex.org/W2106444886","https://openalex.org/W2608622083"],"abstract_inverted_index":{"On-chip":[0],"memory":[1],"organization":[2,146,208],"is":[3,49,59,160],"one":[4],"of":[5,97,127,172],"the":[6,13,21,45,144,164,184,204,213],"most":[7],"important":[8],"aspects":[9],"that":[10,68,147,189],"can":[11,115,174],"influence":[12],"overall":[14],"system":[15,132],"behavior":[16],"in":[17,44,101,183],"multi-processor":[18],"systems.":[19],"Following":[20],"trend":[22],"set":[23,126],"by":[24],"high-performance":[25],"processors,":[26],"high-end":[27],"embedded":[28,46,80],"cores":[29],"are":[30],"moving":[31],"from":[32],"single-level":[33],"on":[34,52,201],"chip":[35],"caches":[36,110],"to":[37,76,84,142,162],"a":[38,62,90,125,130,191],"two-level":[39],"on-chip":[40],"cache":[41,99,145,207],"hierarchy.":[42],"Whereas":[43],"world":[47],"there":[48,58],"general":[50],"consensus":[51],"L1":[53],"private":[54,205],"caches,":[55],"for":[56,70,79,93,129,190],"L2":[57,98,109,166,206],"still":[60,209],"not":[61],"dominant":[63],"architectural":[64],"paradigm.":[65],"Cache":[66],"architectures":[67,100,114],"work":[69],"high":[71],"performance":[72],"computers":[73],"turn":[74],"out":[75],"be":[77,116],"inefficient":[78],"systems":[81],"(mainly":[82],"due":[83],"power-efficiency":[85],"issues).":[86],"This":[87],"paper":[88],"presents":[89],"virtual":[91],"platform":[92],"design":[94],"space":[95],"exploration":[96,141],"low-power":[102],"Multi-Processor-Systems-on-Chip":[103],"(MPSoCs).":[104],"The":[105],"tool":[106,137,173],"contains":[107],"several":[108],"templates,":[111],"and":[112,168],"new":[113],"easily":[117],"added":[118],"using":[119],"our":[120,136,150],"flexible":[121],"plugin":[122],"system.":[123],"Given":[124],"constrains":[128],"specific":[131],"(power,":[133],"area,":[134],"performance),":[135],"will":[138,187],"perform":[139],"extensive":[140],"find":[143],"best":[148],"suits":[149],"needs.":[151],"Through":[152],"some":[153,178],"practical":[154],"experiments,":[155],"we":[156],"show":[157,188],"how":[158,169],"it":[159],"possible":[161],"select":[163],"optimal":[165],"cache,":[167],"this":[170],"kind":[171],"help":[175],"designers":[176],"avoid":[177],"common":[179],"misconceptions.":[180],"Benchmarking":[181],"results":[182],"experiments":[185],"section":[186],"case":[192],"study":[193],"with":[194],"multiple":[195],"processors":[196],"running":[197],"communicating":[198],"tasks":[199],"allocated":[200],"different":[202],"cores,":[203],"performs":[210],"better":[211],"than":[212],"shared":[214],"one.":[215]},"counts_by_year":[{"year":2016,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}