{"id":"https://openalex.org/W2061901568","doi":"https://doi.org/10.1145/1785481.1785510","title":"Resource-constrained timing-driven link insertion for critical delay reduction","display_name":"Resource-constrained timing-driven link insertion for critical delay reduction","publication_year":2010,"publication_date":"2010-05-16","ids":{"openalex":"https://openalex.org/W2061901568","doi":"https://doi.org/10.1145/1785481.1785510","mag":"2061901568"},"language":"en","primary_location":{"id":"doi:10.1145/1785481.1785510","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071940138","display_name":"Jin-Tai Yan","orcid":"https://orcid.org/0000-0002-7614-2545"},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Jin-Tai Yan","raw_affiliation_strings":["Chung-Hua University, Hsinchu, Taiwan Roc","Chung Hua University, Hsinchu, Taiwan Roc"],"affiliations":[{"raw_affiliation_string":"Chung-Hua University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I59460038"]},{"raw_affiliation_string":"Chung Hua University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I59460038"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100442704","display_name":"Zhiwei Chen","orcid":"https://orcid.org/0000-0002-1634-1745"},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Zhi-Wei Chen","raw_affiliation_strings":["Chung-Hua University, Hsinchu, Taiwan Roc","Chung Hua University, Hsinchu, Taiwan Roc"],"affiliations":[{"raw_affiliation_string":"Chung-Hua University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I59460038"]},{"raw_affiliation_string":"Chung Hua University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I59460038"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5071940138"],"corresponding_institution_ids":["https://openalex.org/I59460038"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12399416,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"119","last_page":"122"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.58826744556427},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.5881126523017883},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5655696392059326},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5373790264129639},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5317432284355164},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.5279979705810547},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5204306244850159},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5171739459037781},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.49321526288986206},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.48692572116851807},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.47949153184890747},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.45995983481407166},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.4185486137866974},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.4089144468307495},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.3150247633457184},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3134033679962158},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.27805402874946594},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15518248081207275},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1442040205001831},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11406815052032471}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.58826744556427},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.5881126523017883},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5655696392059326},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5373790264129639},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5317432284355164},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.5279979705810547},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5204306244850159},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5171739459037781},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.49321526288986206},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.48692572116851807},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.47949153184890747},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.45995983481407166},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.4185486137866974},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.4089144468307495},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.3150247633457184},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3134033679962158},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.27805402874946594},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15518248081207275},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1442040205001831},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11406815052032471},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1785481.1785510","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2047383049","https://openalex.org/W2098800716","https://openalex.org/W2110105538","https://openalex.org/W2113959782","https://openalex.org/W2119165650","https://openalex.org/W2126226073","https://openalex.org/W2168150082","https://openalex.org/W2542641932","https://openalex.org/W6729209755"],"related_works":["https://openalex.org/W2145535176","https://openalex.org/W1570180536","https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W1804063983","https://openalex.org/W2134944363","https://openalex.org/W2122901855","https://openalex.org/W2087387686","https://openalex.org/W3140640533","https://openalex.org/W2117925677"],"abstract_inverted_index":{"For":[0],"timing-driven":[1,86,93],"or":[2,69],"yield-driven":[3],"designs,":[4],"non-tree":[5,47],"routing":[6],"has":[7,53,122],"become":[8],"more":[9,11],"and":[10,13,125,146],"popular":[12],"additional":[14],"loops":[15],"provide":[16],"the":[17,23,26,31,46,62,97,101,123,129,133,136,144,151],"redundant":[18],"paths":[19],"to":[20,91,95],"protect":[21],"against":[22],"effect":[24],"of":[25,33,49,64,100,128,150],"open":[27,37],"defects.":[28],"Based":[29],"on":[30,61,132],"assumption":[32],"a":[34,39,50,66,72,78,105,110],"single":[35],"wiring":[36],"in":[38,71,104,139],"signal":[40,51],"net,":[41],"it":[42],"is":[43,89],"known":[44],"that":[45,118],"interconnection":[48],"net":[52],"no":[54],"adjacent":[55],"loop.":[56],"In":[57],"this":[58],"paper,":[59],"based":[60],"concept":[63],"splitting":[65],"time-equivalent":[67],"node":[68],"edge":[70],"cyclic":[73],"connection":[74],"for":[75,84,135],"timing":[76],"analysis,":[77],"0-1":[79],"integer":[80],"linear":[81],"programming(ILP)":[82],"formulation":[83],"resource-constrained":[85],"link":[87],"insertion":[88],"proposed":[90,120],"insert":[92],"links":[94],"maximize":[96],"reduced":[98],"delay":[99,131],"critical":[102,130],"path":[103],"rectilinear":[106],"Steiner":[107],"tree":[108],"under":[109,143],"given":[111],"resource":[112,148],"constraint.":[113],"The":[114],"experimental":[115],"results":[116],"show":[117],"our":[119],"algorithm":[121],"21.0%":[124],"23.5%":[126],"reduction":[127],"average":[134],"tested":[137],"trees":[138],"reasonable":[140],"CPU":[141],"time":[142],"10%":[145],"20%":[147],"constraint":[149],"total":[152],"wirelength,":[153],"respectively.":[154]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
