{"id":"https://openalex.org/W2013877738","doi":"https://doi.org/10.1145/1785481.1785508","title":"A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths","display_name":"A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths","publication_year":2010,"publication_date":"2010-05-16","ids":{"openalex":"https://openalex.org/W2013877738","doi":"https://doi.org/10.1145/1785481.1785508","mag":"2013877738"},"language":"en","primary_location":{"id":"doi:10.1145/1785481.1785508","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785508","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102119602","display_name":"Keisuke Inoue","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Keisuke Inoue","raw_affiliation_strings":["Japan Advanced Institute of Science and Technology, Nomi, Japan"],"affiliations":[{"raw_affiliation_string":"Japan Advanced Institute of Science and Technology, Nomi, Japan","institution_ids":["https://openalex.org/I177738480"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112420841","display_name":"Mineo Kaneko","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Mineo Kaneko","raw_affiliation_strings":["Japan Advanced Institute of Science and Technology, Nomi, Japan"],"affiliations":[{"raw_affiliation_string":"Japan Advanced Institute of Science and Technology, Nomi, Japan","institution_ids":["https://openalex.org/I177738480"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5102119602"],"corresponding_institution_ids":["https://openalex.org/I177738480"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08833376,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"111","last_page":"114"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.789607048034668},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7573683857917786},{"id":"https://openalex.org/keywords/shared-resource","display_name":"Shared resource","score":0.6648814678192139},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6301411986351013},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5688226222991943},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5237181782722473},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5012948513031006},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.45615023374557495},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.4371417164802551},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.4310573935508728},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.40088656544685364},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.336376428604126},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.32779017090797424},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.31200242042541504},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.21922975778579712},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.17983219027519226},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.1445690393447876},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07882526516914368}],"concepts":[{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.789607048034668},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7573683857917786},{"id":"https://openalex.org/C51332947","wikidata":"https://www.wikidata.org/wiki/Q1172305","display_name":"Shared resource","level":2,"score":0.6648814678192139},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6301411986351013},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5688226222991943},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5237181782722473},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5012948513031006},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.45615023374557495},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.4371417164802551},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.4310573935508728},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.40088656544685364},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.336376428604126},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.32779017090797424},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.31200242042541504},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.21922975778579712},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.17983219027519226},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.1445690393447876},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07882526516914368},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1785481.1785508","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785508","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1558331362","https://openalex.org/W1593445040","https://openalex.org/W2136707402","https://openalex.org/W2152531251"],"related_works":["https://openalex.org/W2064431979","https://openalex.org/W2196541947","https://openalex.org/W2120935739","https://openalex.org/W2123535323","https://openalex.org/W1972821547","https://openalex.org/W2101075828","https://openalex.org/W4233035441","https://openalex.org/W2142474790","https://openalex.org/W4247816723","https://openalex.org/W622253553"],"abstract_inverted_index":{"Considering":[0],"the":[1,23,29,69,73,85,90,93,98],"timing":[2,30],"uncertainty/variation":[3],"of":[4,25,46],"control":[5,32,47],"signals":[6,48],"and":[7,34,51,72,105],"a":[8,16,82,106,114],"clock":[9],"signal":[10],"to":[11,39,49,67],"components,":[12],"this":[13],"paper":[14],"proposes":[15,35],"novel":[17],"resource":[18,36,75,100],"sharing":[19,37,76,101],"model":[20,77,102],"which":[21,42,63],"overcomes":[22],"risks":[24],"malfunctions":[26],"caused":[27],"by":[28,122],"problems.":[31],"timings,":[33],"conditions":[38],"FU":[40],"assignment,":[41],"guarantee":[43,68],"correct":[44,70],"timings":[45],"multiplexers":[50],"registers":[52],"under":[53,97],"delay":[54],"uncertainty/variation.":[55],"This":[56],"approach":[57],"is":[58,64,78,81,103,111,120],"combined":[59],"with":[60],"``ordered":[61],"clocking''":[62],"another":[65],"mechanism":[66],"timing,":[71],"final":[74],"devised.":[79],"There":[80],"major":[83],"drawback:":[84],"increase":[86],"in":[87],"latency.":[88],"As":[89],"first":[91],"step,":[92],"latency":[94],"minimization":[95],"problem":[96],"proposed":[99,112,118],"formulated,":[104],"simple":[107],"List":[108],"Scheduling-based":[109],"algorithm":[110],"as":[113],"solution":[115],"algorithm.":[116],"The":[117],"method":[119],"evaluated":[121],"experimental":[123],"results":[124],"for":[125],"some":[126],"benchmark":[127],"circuits.":[128]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
