{"id":"https://openalex.org/W2048967727","doi":"https://doi.org/10.1145/1785481.1785486","title":"Bus via reduction based on floorplan revising","display_name":"Bus via reduction based on floorplan revising","publication_year":2010,"publication_date":"2010-05-16","ids":{"openalex":"https://openalex.org/W2048967727","doi":"https://doi.org/10.1145/1785481.1785486","mag":"2048967727"},"language":"en","primary_location":{"id":"doi:10.1145/1785481.1785486","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071177359","display_name":"Ou He","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Ou He","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110234701","display_name":"Sheqin Dong","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Sheqin Dong","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034755987","display_name":"Jinian Bian","orcid":"https://orcid.org/0000-0002-4322-1503"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinian Bian","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086719215","display_name":"Sotoshi Goto","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Sotoshi Goto","raw_affiliation_strings":["Waseda University, Kitakyushu, Japan"],"affiliations":[{"raw_affiliation_string":"Waseda University, Kitakyushu, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039615312","display_name":"Chung\u2010Kuan Cheng","orcid":"https://orcid.org/0000-0002-9865-8390"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chung-Kuan Cheng","raw_affiliation_strings":["University of California, San Diego, San Diego, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5071177359"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":1.1546,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.80631247,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"9","last_page":"14"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9223282933235168},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7575920820236206},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7559365630149841},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.7259767651557922},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6308292746543884},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6079525351524353},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5306642651557922},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.49581703543663025},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4506979286670685},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44370895624160767},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33802568912506104},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27520182728767395},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.17476803064346313},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17374229431152344},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1467745304107666},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11302107572555542}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9223282933235168},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7575920820236206},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7559365630149841},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.7259767651557922},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6308292746543884},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6079525351524353},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5306642651557922},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.49581703543663025},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4506979286670685},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44370895624160767},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33802568912506104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27520182728767395},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.17476803064346313},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17374229431152344},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1467745304107666},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11302107572555542},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1785481.1785486","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1785481.1785486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 20th symposium on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1820701515","https://openalex.org/W2013245378","https://openalex.org/W2021411243","https://openalex.org/W2041433119","https://openalex.org/W2113837636","https://openalex.org/W2125232865","https://openalex.org/W2133679891","https://openalex.org/W2144473140","https://openalex.org/W2144733697","https://openalex.org/W2150369487","https://openalex.org/W2151335843","https://openalex.org/W2153770483","https://openalex.org/W2163517325","https://openalex.org/W2163929525","https://openalex.org/W2167649713","https://openalex.org/W3165267979","https://openalex.org/W6638487711"],"related_works":["https://openalex.org/W4240503776","https://openalex.org/W2046102945","https://openalex.org/W2167693349","https://openalex.org/W1693171640","https://openalex.org/W2186482337","https://openalex.org/W2018755015","https://openalex.org/W1518650219","https://openalex.org/W1919516409","https://openalex.org/W4211105560","https://openalex.org/W2001838379"],"abstract_inverted_index":{"As":[0],"a":[1,26,31,39,52,67,82],"global":[2],"interconnection,":[3],"bus":[4,15,24],"is":[5,63,91,101,119],"critical":[6],"for":[7],"chip":[8,57],"performance":[9],"in":[10],"deep":[11],"submicron":[12],"technology.":[13],"Reducing":[14],"routing":[16,25,49,88],"vias":[17,50],"will":[18],"facilitate":[19],"the":[20,45,56],"lithography":[21],"and":[22,29,59,73,84,95],"give":[23],"higher":[27,32],"yield":[28],"also":[30,120],"performance.":[33],"In":[34],"this":[35],"paper,":[36],"we":[37],"present":[38],"floorplan":[40],"revising":[41,74,100],"method":[42,80],"to":[43,65,93,103,111,115,122],"minimize":[44],"number":[46],"of":[47,87],"reducible":[48],"with":[51],"controllable":[53],"loss":[54],"on":[55],"area":[58],"wirelength.":[60],"Therefore,":[61],"it":[62],"easy":[64],"make":[66],"proper":[68],"tradeoff":[69],"between":[70],"via":[71],"reduction":[72,86],"loss.":[75],"Experiments":[76],"show":[77],"that":[78],"our":[79,99],"reaches":[81],"96.2%":[83],"93.5%":[85],"vias,":[89],"which":[90,107],"close":[92],"100%":[94],"runs":[96],"fast.":[97],"Besides,":[98],"friendly":[102],"all":[104],"third-party":[105],"floorplanners,":[106],"can":[108],"be":[109],"applied":[110],"any":[112],"existing":[113],"floorplans":[114],"reduce":[116],"vias.":[117],"It":[118],"scalable":[121],"larger":[123],"benchmarks.":[124]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}