{"id":"https://openalex.org/W2145247911","doi":"https://doi.org/10.1145/1741906.1742166","title":"Performance comparison of software and FPGA implementation of computationally intensive algorithms","display_name":"Performance comparison of software and FPGA implementation of computationally intensive algorithms","publication_year":2010,"publication_date":"2010-02-26","ids":{"openalex":"https://openalex.org/W2145247911","doi":"https://doi.org/10.1145/1741906.1742166","mag":"2145247911"},"language":"en","primary_location":{"id":"doi:10.1145/1741906.1742166","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1741906.1742166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference and Workshop on Emerging Trends in Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088743772","display_name":"Laxmikant Bordekar","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Laxmikant Bordekar","raw_affiliation_strings":[""],"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052279124","display_name":"Gajanan Gawde","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Gajanan S. Gawde","raw_affiliation_strings":[""],"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5088743772"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19874206,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1004","last_page":"1004"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9416999816894531,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9416999816894531,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9384999871253967,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11233","display_name":"Advanced Adaptive Filtering Techniques","score":0.9014999866485596,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.8294666409492493},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.8091092705726624},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8021239042282104},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7651835680007935},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5917015671730042},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.58412104845047},{"id":"https://openalex.org/keywords/split-radix-fft-algorithm","display_name":"Split-radix FFT algorithm","score":0.46798941493034363},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.46297141909599304},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.45904630422592163},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.4532051384449005},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4310227930545807},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40637877583503723},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39118629693984985},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37604808807373047},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.13954666256904602},{"id":"https://openalex.org/keywords/fourier-transform","display_name":"Fourier transform","score":0.10251456499099731}],"concepts":[{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.8294666409492493},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.8091092705726624},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8021239042282104},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7651835680007935},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5917015671730042},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.58412104845047},{"id":"https://openalex.org/C103755468","wikidata":"https://www.wikidata.org/wiki/Q17103599","display_name":"Split-radix FFT algorithm","level":5,"score":0.46798941493034363},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.46297141909599304},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.45904630422592163},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4532051384449005},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4310227930545807},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40637877583503723},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39118629693984985},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37604808807373047},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.13954666256904602},{"id":"https://openalex.org/C102519508","wikidata":"https://www.wikidata.org/wiki/Q6520159","display_name":"Fourier transform","level":2,"score":0.10251456499099731},{"id":"https://openalex.org/C166386157","wikidata":"https://www.wikidata.org/wiki/Q1477735","display_name":"Short-time Fourier transform","level":4,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C203024314","wikidata":"https://www.wikidata.org/wiki/Q1365258","display_name":"Fourier analysis","level":3,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1741906.1742166","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1741906.1742166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference and Workshop on Emerging Trends in Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2347617805","https://openalex.org/W2389765791","https://openalex.org/W2351923727","https://openalex.org/W2185259940","https://openalex.org/W2031343199","https://openalex.org/W2377898907","https://openalex.org/W2113951268","https://openalex.org/W2376047108","https://openalex.org/W2168413811","https://openalex.org/W2387826621"],"abstract_inverted_index":{"Fast":[0],"Fourier":[1],"Transforms":[2],"(FFT)":[3],"based":[4],"digital":[5,28,76,98],"signal":[6,13,77,99],"processing":[7],"has":[8,69],"vast":[9],"applications":[10],"in":[11,42,48,116,125,141],"radar":[12],"processing.":[14],"FFT":[15,104,112,124],"can":[16],"be":[17],"performed":[18],"using":[19,134],"a":[20,25,75],"general":[21],"purpose":[22],"computer":[23],"or":[24],"specially":[26],"designed":[27],"hardware.":[29],"It":[30],"is":[31,127,132,139],"important":[32],"to":[33,71,87,96],"analyze":[34],"the":[35,54,102,109,135],"performance":[36],"of":[37,111,120],"such":[38],"computationally":[39],"intensive":[40],"algorithms":[41,115],"hardware":[43,61],"(FPGA)":[44],"and":[45,84,118,138],"software":[46],"implementation":[47,110],"single":[49],"processor":[50],"machines.":[51],"For":[52],"years":[53],"common":[55],"practice":[56],"for":[57],"implementing":[58],"FFTs":[59],"(in":[60],"other":[62],"than":[63],"application":[64],"specific":[65,90],"integrated":[66],"circuits":[67],"(ASIC))":[68],"been":[70],"run":[72],"them":[73],"on":[74],"processor.":[78],"But":[79],"as":[80,101],"FPGAs":[81,93],"have":[82,85],"evolved":[83],"begun":[86],"accommodate":[88],"function":[89],"computing":[91],"cores,":[92],"are":[94],"beginning":[95],"displace":[97],"processors":[100],"optimum":[103],"solution.":[105],"In":[106],"this":[107],"paper":[108],"radix":[113],"2":[114],"C++":[117],"design":[119,131],"parameterized":[121],"floating":[122],"point":[123],"FPGA":[126],"discussed.":[128],"The":[129],"VERILOG":[130],"tested":[133],"Modelsim":[136],"simulator":[137],"synthesized":[140],"Xilinx":[142],"ISE":[143]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
