{"id":"https://openalex.org/W2082962507","doi":"https://doi.org/10.1145/1741906.1742123","title":"Design of 32 bit (MIPS) RISC PROCESSOR using FPGA","display_name":"Design of 32 bit (MIPS) RISC PROCESSOR using FPGA","publication_year":2010,"publication_date":"2010-02-26","ids":{"openalex":"https://openalex.org/W2082962507","doi":"https://doi.org/10.1145/1741906.1742123","mag":"2082962507"},"language":"en","primary_location":{"id":"doi:10.1145/1741906.1742123","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1741906.1742123","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference and Workshop on Emerging Trends in Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090734026","display_name":"R. M. Kubde","orcid":null},"institutions":[{"id":"https://openalex.org/I4210106255","display_name":"Yashwantrao Chavan Maharashtra Open University","ror":"https://ror.org/01kxpxf76","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210106255"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"R. M. Kubde","raw_affiliation_strings":["Yeshwantrao Chavan College Of Engg., Nagpur, India","[Yeshwantrao chavan college of Engineering, Nagpur, India]"],"affiliations":[{"raw_affiliation_string":"Yeshwantrao Chavan College Of Engg., Nagpur, India","institution_ids":[]},{"raw_affiliation_string":"[Yeshwantrao chavan college of Engineering, Nagpur, India]","institution_ids":["https://openalex.org/I4210106255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103045666","display_name":"D. B. Bhoyar","orcid":"https://orcid.org/0000-0002-7549-811X"},"institutions":[{"id":"https://openalex.org/I4210106255","display_name":"Yashwantrao Chavan Maharashtra Open University","ror":"https://ror.org/01kxpxf76","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210106255"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"D. B. Bhoyar","raw_affiliation_strings":["Yeshwantrao Chavan College Of Engg., Nagpur, India","[Yeshwantrao chavan college of Engineering, Nagpur, India]"],"affiliations":[{"raw_affiliation_string":"Yeshwantrao Chavan College Of Engg., Nagpur, India","institution_ids":[]},{"raw_affiliation_string":"[Yeshwantrao chavan college of Engineering, Nagpur, India]","institution_ids":["https://openalex.org/I4210106255"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018070606","display_name":"R. S. Khedikar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210106255","display_name":"Yashwantrao Chavan Maharashtra Open University","ror":"https://ror.org/01kxpxf76","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210106255"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. S. Khedikar","raw_affiliation_strings":["Yeshwantrao Chavan College Of Engg., Nagpur, India","[Yeshwantrao chavan college of Engineering, Nagpur, India]"],"affiliations":[{"raw_affiliation_string":"Yeshwantrao Chavan College Of Engg., Nagpur, India","institution_ids":[]},{"raw_affiliation_string":"[Yeshwantrao chavan college of Engineering, Nagpur, India]","institution_ids":["https://openalex.org/I4210106255"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5090734026"],"corresponding_institution_ids":["https://openalex.org/I4210106255"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14146671,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"936","last_page":"939"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9779000282287598,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9779000282287598,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9273999929428101,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8093641400337219},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7733114957809448},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6724461913108826},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6541673541069031},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6126179695129395},{"id":"https://openalex.org/keywords/video-graphics-array","display_name":"Video Graphics Array","score":0.5162906050682068},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5111148953437805},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5027256011962891},{"id":"https://openalex.org/keywords/32-bit","display_name":"32-bit","score":0.45946004986763},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4313455820083618},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4236152172088623},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3433181047439575},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.30274930596351624}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8093641400337219},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7733114957809448},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6724461913108826},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6541673541069031},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6126179695129395},{"id":"https://openalex.org/C139983466","wikidata":"https://www.wikidata.org/wiki/Q17194","display_name":"Video Graphics Array","level":3,"score":0.5162906050682068},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5111148953437805},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5027256011962891},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.45946004986763},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4313455820083618},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4236152172088623},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3433181047439575},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.30274930596351624}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1741906.1742123","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1741906.1742123","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference and Workshop on Emerging Trends in Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W1543077104"],"related_works":["https://openalex.org/W3200876981","https://openalex.org/W1602030439","https://openalex.org/W2375524523","https://openalex.org/W2538139389","https://openalex.org/W2994098388","https://openalex.org/W2135839484","https://openalex.org/W2360644583","https://openalex.org/W1558672475","https://openalex.org/W2104103961","https://openalex.org/W2941899821"],"abstract_inverted_index":{"The":[0,13,79,98],"proposed":[1],"work":[2,121],"is":[3,15,43,73,93,168],"aimed":[4],"at":[5],"designing":[6,94],"general":[7],"purpose":[8],"32":[9],"bit":[10],"RISC(MIPS)":[11,96],"processor.":[12,97],"system":[14,133],"design":[16,100],"using":[17,137],"VHDL":[18,144],"language":[19],"and":[20,129,134,148],"this":[21,91],"source":[22,80],"code":[23,81],"can":[24,33,82],"be":[25,34,57,84],"use":[26],"as":[27],"IP":[28],"(Intellectual":[29],"Property)":[30],"core":[31],"which":[32],"targeted":[35],"to":[36,56,75,103,126,170],"any":[37],"FPGA":[38,60],"for":[39,86,179],"several":[40],"applications.":[41],"Emphasis":[42],"given":[44],"on":[45,59],"simple":[46],"working":[47],"solution":[48],"with":[49,139,153],"minimum":[50],"possible":[51],"area.":[52],"RISC":[53,99],"processor":[54,72,112],"has":[55],"implemented":[58],"(Field":[61],"Programmable":[62],"Gate":[63],"Array)...":[64],"It":[65],"uses":[66],"different":[67],"instructions.":[68],"Simulation":[69],"of":[70,90,142],"entire":[71],"done":[74],"verify":[76],"the":[77,110,115,165,177],"functionality.":[78],"also":[83],"verified":[85],"synthesis":[87],"purpose.":[88],"Objective":[89],"project":[92],"32-bit":[95],"ideally":[101],"suited":[102],"participate":[104],"in":[105,109],"a":[106,149,154,180],"powerful":[107],"trend":[108],"embedded":[111],"market":[113],"--":[114],"\"system-on-a-chip\".":[116],"This":[117],"paper":[118],"describes":[119],"current":[120],"utilizing":[122],"rapid":[123],"prototyping":[124],"approach":[125],"simulate,":[127],"synthesize,":[128],"implement":[130],"prototype":[131],"digital":[132],"computer":[135],"architectures":[136],"PCs":[138],"student":[140],"versions":[141],"commercial":[143],"based":[145],"CAD":[146],"tools":[147],"low":[150],"cost":[151],"board":[152],"large":[155],"CPLD":[156,166],"or":[157,173],"FPGA.":[158],"VGA":[159],"video":[160],"output":[161],"generated":[162],"directly":[163],"by":[164],"chip":[167],"used":[169],"display":[171],"graphics":[172],"textual":[174],"data":[175],"eliminating":[176],"need":[178],"logic":[181],"analyzer.":[182]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
