{"id":"https://openalex.org/W4214773815","doi":"https://doi.org/10.1145/1736020.1736023","title":"Dynamically replicated memory","display_name":"Dynamically replicated memory","publication_year":2010,"publication_date":"2010-03-13","ids":{"openalex":"https://openalex.org/W4214773815","doi":"https://doi.org/10.1145/1736020.1736023"},"language":"en","primary_location":{"id":"doi:10.1145/1736020.1736023","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1736020.1736023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032587556","display_name":"Engin \u0130pek","orcid":"https://orcid.org/0000-0003-2809-5809"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Engin Ipek","raw_affiliation_strings":["University of Rochester, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037548097","display_name":"Jeremy Condit","orcid":null},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeremy Condit","raw_affiliation_strings":["Microsoft Research, Redmond, WA, USA"],"affiliations":[{"raw_affiliation_string":"Microsoft Research, Redmond, WA, USA","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031385754","display_name":"Edmund B. Nightingale","orcid":null},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Edmund B. Nightingale","raw_affiliation_strings":["Microsoft Research, Redmond, WA, USA"],"affiliations":[{"raw_affiliation_string":"Microsoft Research, Redmond, WA, USA","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067337700","display_name":"Doug Burger","orcid":"https://orcid.org/0009-0006-6588-6596"},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Doug Burger","raw_affiliation_strings":["Microsoft Research, Redmond, WA, USA"],"affiliations":[{"raw_affiliation_string":"Microsoft Research, Redmond, WA, USA","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041937385","display_name":"Thomas Moscibroda","orcid":"https://orcid.org/0000-0002-8729-7841"},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Thomas Moscibroda","raw_affiliation_strings":["Microsoft Research, Redmond, WA, USA"],"affiliations":[{"raw_affiliation_string":"Microsoft Research, Redmond, WA, USA","institution_ids":["https://openalex.org/I1290206253"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5032587556"],"corresponding_institution_ids":["https://openalex.org/I5388228"],"apc_list":null,"apc_paid":null,"fwci":14.5837,"has_fulltext":false,"cited_by_count":129,"citation_normalized_percentile":{"value":0.99182484,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"3","last_page":"14"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9618821144104004},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.8376522660255432},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.7931472659111023},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7348691821098328},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5593822002410889},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.5583740472793579},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.45221036672592163},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.4213506877422333},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4144071936607361},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.40127119421958923},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3240373432636261},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3158338665962219},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21306216716766357},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.19281232357025146},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.17356735467910767},{"id":"https://openalex.org/keywords/phase-change","display_name":"Phase change","score":0.15839964151382446},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15609273314476013},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12913143634796143},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.09793728590011597},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09381958842277527},{"id":"https://openalex.org/keywords/engineering-physics","display_name":"Engineering physics","score":0.06937301158905029}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9618821144104004},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.8376522660255432},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.7931472659111023},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7348691821098328},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5593822002410889},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.5583740472793579},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.45221036672592163},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.4213506877422333},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4144071936607361},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.40127119421958923},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3240373432636261},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3158338665962219},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21306216716766357},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.19281232357025146},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.17356735467910767},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.15839964151382446},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15609273314476013},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12913143634796143},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.09793728590011597},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09381958842277527},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.06937301158905029}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1736020.1736023","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1736020.1736023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1627476744","https://openalex.org/W1767399337","https://openalex.org/W1987201308","https://openalex.org/W2003813631","https://openalex.org/W2008298020","https://openalex.org/W2048588974","https://openalex.org/W2056641105","https://openalex.org/W2059879891","https://openalex.org/W2064977311","https://openalex.org/W2102449048","https://openalex.org/W2110321764","https://openalex.org/W2112753327","https://openalex.org/W2114139104","https://openalex.org/W2117702591","https://openalex.org/W2135393827","https://openalex.org/W2138436606","https://openalex.org/W2144603794","https://openalex.org/W2149122124","https://openalex.org/W2149720761","https://openalex.org/W2157808045","https://openalex.org/W6636642913"],"related_works":["https://openalex.org/W264943428","https://openalex.org/W2074922484","https://openalex.org/W4283326582","https://openalex.org/W2094308961","https://openalex.org/W2473808647","https://openalex.org/W4386903460","https://openalex.org/W2178010602","https://openalex.org/W2268596372","https://openalex.org/W3004383742","https://openalex.org/W2126830366"],"abstract_inverted_index":{"DRAM":[0,34,39],"is":[1,43],"facing":[2],"severe":[3],"scalability":[4],"challenges":[5],"in":[6,20],"sub-45nm":[7],"tech-":[8],"nology":[9],"nodes":[10],"due":[11],"to":[12,48],"precise":[13],"charge":[14],"placement":[15],"and":[16,35,45],"sensing":[17],"hur-":[18],"dles":[19],"deep-submicron":[21],"geometries.":[22],"Resistive":[23],"memories,":[24],"such":[25],"as":[26],"phase-change":[27],"memory":[28],"(PCM),":[29],"already":[30],"scale":[31],"well":[32],"beyond":[33],"are":[36],"a":[37],"promising":[38],"replacement.":[40],"Unfortunately,":[41],"PCM":[42,56],"write-limited,":[44],"current":[46],"approaches":[47],"managing":[49],"writes":[50],"must":[51],"de-":[52],"commission":[53],"pages":[54],"of":[55],"when":[57],"the":[58],"first":[59],"bit":[60],"fails.":[61]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":8},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":15},{"year":2014,"cited_by_count":25},{"year":2013,"cited_by_count":22},{"year":2012,"cited_by_count":16}],"updated_date":"2026-03-06T13:50:29.536080","created_date":"2025-10-10T00:00:00"}
