{"id":"https://openalex.org/W2055394412","doi":"https://doi.org/10.1145/1735023.1735062","title":"Performance study of VeSFET-based, high-density regular circuits","display_name":"Performance study of VeSFET-based, high-density regular circuits","publication_year":2010,"publication_date":"2010-03-14","ids":{"openalex":"https://openalex.org/W2055394412","doi":"https://doi.org/10.1145/1735023.1735062","mag":"2055394412"},"language":"en","primary_location":{"id":"doi:10.1145/1735023.1735062","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1735023.1735062","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th international symposium on Physical design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064821922","display_name":"Yi-Wei Lin","orcid":"https://orcid.org/0000-0001-8047-1977"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yi-Wei Lin","raw_affiliation_strings":["University of California, Santa Barbara, Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063371595","display_name":"Malgorzata Marek-Sadowska","orcid":"https://orcid.org/0000-0002-3934-7031"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malgorzata Marek-Sadowska","raw_affiliation_strings":["University of California, Santa Barbara, Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013238154","display_name":"W. Maly","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wojciech Maly","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA, USA","Carnegie-Mellon University, Pittsburgh, Pa., USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie-Mellon University, Pittsburgh, Pa., USA#TAB#","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5885,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72211435,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"161","last_page":"168"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7551797032356262},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6763001084327698},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6371108293533325},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6163318157196045},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6148638725280762},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5091528296470642},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.447486937046051},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4297182261943817},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41170182824134827},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.312652587890625},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2587166428565979},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21282914280891418},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17997905611991882},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14614567160606384},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10702410340309143}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7551797032356262},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6763001084327698},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6371108293533325},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6163318157196045},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6148638725280762},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5091528296470642},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.447486937046051},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4297182261943817},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41170182824134827},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.312652587890625},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2587166428565979},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21282914280891418},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17997905611991882},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14614567160606384},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10702410340309143},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1735023.1735062","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1735023.1735062","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th international symposium on Physical design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1492192095","https://openalex.org/W1511688816","https://openalex.org/W1527113684","https://openalex.org/W1987067207","https://openalex.org/W2035368095","https://openalex.org/W2041176678","https://openalex.org/W2100344939","https://openalex.org/W2116625560","https://openalex.org/W2141803235","https://openalex.org/W2151254956","https://openalex.org/W6630623413"],"related_works":["https://openalex.org/W3090875125","https://openalex.org/W2091329789","https://openalex.org/W2143608234","https://openalex.org/W2111071331","https://openalex.org/W2119373721","https://openalex.org/W2134385741","https://openalex.org/W4200577934","https://openalex.org/W1538254313","https://openalex.org/W2626325543","https://openalex.org/W2251104045"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,106],"study":[4],"circuits":[5],"implemented":[6],"using":[7],"high-density":[8],"arrays":[9],"composed":[10],"of":[11,65,91],"Vertical":[12],"Slit":[13],"Field":[14],"Effect":[15],"Transistors.":[16],"This":[17],"layout":[18],"style":[19],"could":[20],"dramatically":[21],"increase":[22,64],"transistor":[23,38],"density":[24],"and":[25,40,86,102],"therefore":[26],"reduce":[27],"fabrication":[28],"cost.":[29],"However,":[30],"its":[31],"geometrical":[32],"restrictions,":[33],"imposed":[34],"by":[35,80,87],"the":[36,66,100],"super-regular":[37],"arrangement":[39],"strictly":[41],"parallel":[42],"metal":[43,93,103],"tracks":[44],"pose":[45],"new":[46],"design":[47],"challenges.":[48],"Our":[49],"experiments":[50],"reveal":[51],"that":[52,73],"very":[53],"dense":[54],"cell-level":[55],"interconnect":[56,84],"pattern":[57],"may":[58],"be":[59,78],"responsible":[60],"for":[61,95,112],"unnecessary":[62],"15%":[63],"circuit-level,":[67],"critical":[68,113],"path":[69],"delays.":[70],"We":[71],"demonstrate":[72],"these":[74],"extra":[75],"delays":[76],"can":[77],"avoided":[79],"constructing":[81],"appropriate":[82],"cell":[83],"layouts":[85],"more":[88],"flexible":[89],"usage":[90],"available":[92],"layers":[94],"intra-cell":[96],"routing.":[97],"To":[98],"balance":[99],"performance":[101],"layer":[104],"usage,":[105],"propose":[107],"a":[108],"linear":[109],"programming-based":[110],"technique":[111],"net":[114],"re-routing.":[115]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
