{"id":"https://openalex.org/W2031630683","doi":"https://doi.org/10.1145/1723112.1723184","title":"DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only)","display_name":"DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only)","publication_year":2010,"publication_date":"2010-02-21","ids":{"openalex":"https://openalex.org/W2031630683","doi":"https://doi.org/10.1145/1723112.1723184","mag":"2031630683"},"language":"en","primary_location":{"id":"doi:10.1145/1723112.1723184","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723184","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065412990","display_name":"Yangyang Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yangyang Pan","raw_affiliation_strings":["Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100378782","display_name":"Tong Zhang","orcid":"https://orcid.org/0000-0002-3481-6062"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tong Zhang","raw_affiliation_strings":["Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5065412990"],"corresponding_institution_ids":["https://openalex.org/I165799507"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10123656,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"290","last_page":"290"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9053354263305664},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7799443006515503},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7402973771095276},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.69899982213974},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.6778437495231628},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6578898429870605},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.618793249130249},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4998645782470703},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4979679584503174},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.4628225266933441},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.4571947157382965},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.43881362676620483},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.43553340435028076},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4163532555103302},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3403659164905548},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3240910470485687},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.32188284397125244},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.31098324060440063},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.22586682438850403}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9053354263305664},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7799443006515503},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7402973771095276},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.69899982213974},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.6778437495231628},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6578898429870605},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.618793249130249},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4998645782470703},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4979679584503174},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.4628225266933441},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.4571947157382965},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.43881362676620483},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.43553340435028076},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4163532555103302},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3403659164905548},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3240910470485687},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.32188284397125244},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.31098324060440063},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.22586682438850403},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1723112.1723184","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723184","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1504875048","https://openalex.org/W1505220924","https://openalex.org/W1523051745","https://openalex.org/W1973062518","https://openalex.org/W1984588379","https://openalex.org/W1996444152","https://openalex.org/W2034879482","https://openalex.org/W2038061869","https://openalex.org/W2038355886","https://openalex.org/W2042350992","https://openalex.org/W2045617353","https://openalex.org/W2068284571","https://openalex.org/W2083007561","https://openalex.org/W2088072859","https://openalex.org/W2093341341","https://openalex.org/W2094915857","https://openalex.org/W2095841863","https://openalex.org/W2131055836","https://openalex.org/W2141473386","https://openalex.org/W2143169838","https://openalex.org/W2144149750","https://openalex.org/W2146185334","https://openalex.org/W2170510975","https://openalex.org/W6600310816"],"related_works":["https://openalex.org/W1494152240","https://openalex.org/W1030357071","https://openalex.org/W2171888576","https://openalex.org/W2123815799","https://openalex.org/W2188534734","https://openalex.org/W2077606475","https://openalex.org/W2136485767","https://openalex.org/W1981423095","https://openalex.org/W1572401189","https://openalex.org/W4238754064"],"abstract_inverted_index":{"Motivated":[0],"by":[1,110],"the":[2,11,80,121],"emerging":[3],"three-dimensional":[4],"(3D":[5],"integration":[6],"technologies,":[7],"this":[8,101],"paper":[9],"studies":[10],"potential":[12,116],"of":[13,89],"applying":[14],"3D":[15,64,81,111],"memory":[16,66,83,112],"stacking":[17,113],"to":[18,26,125],"enable":[19,95],"FPGA":[20,69,97,107,133],"devices":[21],"use":[22,37,62],"on-chip":[23,38,47,76],"DRAM":[24,39,48,52,77],"cells":[25,40],"store":[27,86],"configuration":[28,42,70,90],"data.":[29],"In":[30,100],"current":[31],"design":[32,108,117],"practice,":[33],"FPGAs":[34,129],"do":[35],"not":[36],"for":[41],"data":[43,71],"storage":[44,72],"mainly":[45],"because":[46],"self-refreshing":[49],"involves":[50],"destructive":[51],"read":[53],"operations.":[54],"This":[55],"problem":[56],"can":[57,84,93,130],"be":[58],"solved":[59],"if":[60],"we":[61,103],"a":[63],"stacked":[65,82],"as":[67],"primary":[68],"and":[73,114,119,136,140],"externally":[74],"refresh":[75],"cells.":[78],"Since":[79],"easily":[85],"multiple":[87],"sets":[88],"data,":[91],"it":[92],"meanwhile":[94],"high-speed":[96],"dynamic":[98],"reconfiguration.":[99],"paper,":[102],"study":[104],"such":[105],"DRAM-based":[106,128],"enabled":[109],"investigate":[115],"issues,":[118],"employ":[120],"VPR":[122],"tool":[123],"set":[124],"demonstrate":[126],"that":[127],"noticeably":[131],"reduce":[132],"die":[134],"area":[135],"hence":[137],"improve":[138],"speed":[139],"energy":[141],"consumption":[142],"performance,":[143],"compared":[144],"their":[145],"SRAM-based":[146],"counterparts.":[147]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
