{"id":"https://openalex.org/W1980616461","doi":"https://doi.org/10.1145/1723112.1723178","title":"Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only)","display_name":"Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only)","publication_year":2010,"publication_date":"2010-02-21","ids":{"openalex":"https://openalex.org/W1980616461","doi":"https://doi.org/10.1145/1723112.1723178","mag":"1980616461"},"language":"en","primary_location":{"id":"doi:10.1145/1723112.1723178","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723178","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053471252","display_name":"Amir Masoud Gharehbaghi","orcid":"https://orcid.org/0000-0002-0451-221X"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Amir Masoud Gharehbaghi","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069623023","display_name":"Bijan Alizadeh","orcid":"https://orcid.org/0000-0003-4436-4597"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Bijan Alizadeh","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5053471252"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06774598,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"288","last_page":"288"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7640672326087952},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7613956928253174},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6971309185028076},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6210355758666992},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6024782657623291},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5866333842277527},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5628540515899658},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.510955274105072},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.44818544387817383},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.41256090998649597},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3426744341850281},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3350624442100525},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31454116106033325},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2811964154243469},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22536468505859375},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.07385218143463135},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.06489047408103943}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7640672326087952},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7613956928253174},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6971309185028076},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6210355758666992},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6024782657623291},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5866333842277527},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5628540515899658},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.510955274105072},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.44818544387817383},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.41256090998649597},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3426744341850281},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3350624442100525},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31454116106033325},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2811964154243469},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22536468505859375},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.07385218143463135},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.06489047408103943},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1723112.1723178","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723178","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2116514610","https://openalex.org/W2891365107","https://openalex.org/W4380363361","https://openalex.org/W3201048403","https://openalex.org/W2138768308","https://openalex.org/W2003180247","https://openalex.org/W4235807419","https://openalex.org/W2144633290","https://openalex.org/W2144282137","https://openalex.org/W2166758053"],"abstract_inverted_index":{"Clock":[0],"period":[1],"of":[2,24,88,93,97,124,139,162,165],"pipelined":[3,71,89,130,214],"designs":[4,90],"are":[5,58,167],"usually":[6],"determined":[7],"by":[8,127,155],"the":[9,25,30,37,48,54,62,106,113,118,122,134,152,158,195,204,222],"critical":[10,49,55],"paths":[11,50],"to":[12,33,109],"avoid":[13],"timing":[14,80,98,159,175,183],"errors":[15,99],"and":[16,53,186],"guarantee":[17],"reliable":[18,86],"operations.":[19],"The":[20,174],"worst":[21,114],"case":[22],"delays":[23,57,220],"slowest":[26],"pipeline":[27,102],"stages":[28],"cause":[29],"clock":[31,107,153],"frequency":[32,108,154],"be":[34,110,229],"less":[35],"than":[36,61,112],"average":[38,63],"path":[39,56,64,219],"delays.":[40],"This":[41],"may":[42],"introduce":[43],"enormous":[44],"performance":[45,172,226],"loss":[46],"if":[47],"rarely":[51],"happen,":[52],"far":[59],"larger":[60],"delays,":[65],"which":[66,166,217],"is":[67,201],"common":[68],"for":[69,182,198,213],"many":[70],"circuits.":[72],"In":[73],"this":[74],"paper":[75],"we":[76,148],"present":[77],"a":[78,129,140],"novel":[79],"error":[81,160,176,184],"recovery":[82,177],"technique":[83,126,136],"that":[84,147],"guarantees":[85],"operation":[87],"in":[91,100,221],"presence":[92],"any":[94],"arbitrary":[95],"number":[96],"different":[101],"stages.":[103],"We":[104,120],"allow":[105],"higher":[111],"case;":[115],"hence":[116],"increasing":[117],"performance.":[119],"demonstrate":[121],"usefulness":[123],"our":[125],"implementing":[128],"arithmetic":[131,215],"circuit":[132],"with":[133,157,170,193],"proposed":[135],"on":[137],"top":[138],"FPGA":[141],"board.":[142],"Our":[143],"experimental":[144,205],"results":[145,206],"show":[146],"could":[149],"successfully":[150],"increase":[151],"30%":[156],"rate":[161],"13%,":[163],"all":[164],"automatically":[168],"corrected":[169],"negligible":[171],"penalty.":[173],"circuits":[178,216],"need":[179],"extra":[180,196],"flipflops":[181,200],"detection":[185],"correction.":[187],"Since":[188],"typical":[189],"FPGAs":[190],"have":[191,207],"LUT":[192],"flipflops,":[194],"area":[197],"additional":[199],"minimized":[202],"as":[203],"shown.":[208],"With":[209],"sophisticated":[210],"synthesis":[211],"algorithms":[212],"balanced":[218],"circuits,":[223],"significantly":[224],"more":[225],"improvements":[227],"can":[228],"expected.":[230]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
