{"id":"https://openalex.org/W2075721474","doi":"https://doi.org/10.1145/1723112.1723174","title":"Multiplier architectures for FPGA double precision functions (abstract only)","display_name":"Multiplier architectures for FPGA double precision functions (abstract only)","publication_year":2010,"publication_date":"2010-02-21","ids":{"openalex":"https://openalex.org/W2075721474","doi":"https://doi.org/10.1145/1723112.1723174","mag":"2075721474"},"language":"en","primary_location":{"id":"doi:10.1145/1723112.1723174","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723174","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049652417","display_name":"Y. Hamid","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Y. Hamid","raw_affiliation_strings":["Altera Corporation, Penang, Malaysia","Altera Corporation, Penang, Malaysia#TAB#"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, Penang, Malaysia","institution_ids":[]},{"raw_affiliation_string":"Altera Corporation, Penang, Malaysia#TAB#","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082265695","display_name":"Martin Langhammer","orcid":"https://orcid.org/0000-0001-8206-2077"},"institutions":[{"id":"https://openalex.org/I4210094575","display_name":"Altera (United Kingdom)","ror":"https://ror.org/00m96gg93","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210094575"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Martin Langhammer","raw_affiliation_strings":["Altera Corporation, High Wycombe, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, High Wycombe, United Kingdom","institution_ids":["https://openalex.org/I4210094575"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5049652417"],"corresponding_institution_ids":["https://openalex.org/I22433950"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14329953,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"287","last_page":"287"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9901000261306763,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.8754963874816895},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7296928763389587},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6444724798202515},{"id":"https://openalex.org/keywords/analog-multiplier","display_name":"Analog multiplier","score":0.44950851798057556},{"id":"https://openalex.org/keywords/elementary-function","display_name":"Elementary function","score":0.4112108647823334},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.38713154196739197},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.36512964963912964},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.351739764213562},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33177822828292847},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24212601780891418}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.8754963874816895},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7296928763389587},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6444724798202515},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.44950851798057556},{"id":"https://openalex.org/C182408441","wikidata":"https://www.wikidata.org/wiki/Q824282","display_name":"Elementary function","level":2,"score":0.4112108647823334},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.38713154196739197},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.36512964963912964},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.351739764213562},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33177822828292847},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24212601780891418},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1723112.1723174","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723174","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1876592433","https://openalex.org/W2083269738","https://openalex.org/W2089088242","https://openalex.org/W2145104756","https://openalex.org/W2343687813","https://openalex.org/W2113697565","https://openalex.org/W2760424941","https://openalex.org/W1965508384","https://openalex.org/W2997198572","https://openalex.org/W2117233677"],"abstract_inverted_index":{"FPGA":[0],"devices":[1],"are":[2,16,40],"now":[3,41],"more":[4],"capable":[5],"at":[6],"supporting":[7],"floating":[8],"point":[9],"applications,":[10],"but":[11],"double":[12,76],"precision":[13,33,77],"IEEE754":[14],"systems":[15],"still":[17],"very":[18],"challenging":[19],"to":[20,80,87,149,163],"implement,":[21],"with":[22,83,143,147,166],"large":[23,135],"amounts":[24],"of":[25,64,74,93,117,174],"logic,":[26],"routing,":[27],"and":[28,53,101,114],"DSP":[29],"resources":[30,160],"needed.":[31],"Double":[32],"multiplier":[34,38,48,59,84,96,122,136,152,155,159],"operators,":[35],"requiring":[36],"54x54":[37],"cores,":[39],"directly":[42],"supported":[43],"in":[44,62,171],"the":[45,72,94,111,118,140,158,172],"fabric,":[46],"however,":[47],"based":[49],"algorithms":[50,103],"for":[51],"algebraic":[52],"elementary":[54],"functions":[55],"typically":[56,61],"require":[57],"larger":[58,95],"functions,":[60],"excess":[63],"60x60":[65],"bits":[66],"precision.":[67],"This":[68],"paper":[69],"will":[70,104,131,156],"use":[71],"example":[73],"a":[75,126,167],"exp":[78,119],"(ex)":[79],"explore":[81],"tradeoffs":[82],"architectures":[85,137],"mapped":[86],"current":[88],"FPGAs":[89],"devices.":[90],"Different":[91],"types":[92],"architectures,":[97,123],"including":[98,107],"direct":[99],"implementations":[100],"Karatsuba-Ofman":[102],"be":[105,133],"compared,":[106],"their":[108],"effect":[109],"on":[110],"resource":[112],"requirements":[113],"system":[115,145],"performance":[116],"function.":[120],"Smaller":[121,154],"which":[124],"introduce":[125],"small":[127,168],"maximum":[128,169],"functional":[129],"error,":[130,170],"also":[132],"examined.Alternate":[134],"can":[138],"provide":[139],"same":[141],"accuracy":[142],"increased":[144],"performance,":[146],"up":[148,162],"33%":[150],"less":[151],"resources.":[153],"reduce":[157],"by":[161],"50%,":[164],"albeit":[165],"range":[173],"5":[175],"ulp.":[176]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
