{"id":"https://openalex.org/W2123284420","doi":"https://doi.org/10.1145/1723112.1723172","title":"Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only)","display_name":"Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only)","publication_year":2010,"publication_date":"2010-02-21","ids":{"openalex":"https://openalex.org/W2123284420","doi":"https://doi.org/10.1145/1723112.1723172","mag":"2123284420"},"language":"en","primary_location":{"id":"doi:10.1145/1723112.1723172","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723172","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5105839606","display_name":"Arpith C. Jacob","orcid":null},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Arpith C. Jacob","raw_affiliation_strings":["Washington University in St. Louis, St. Louis, MO, USA"],"affiliations":[{"raw_affiliation_string":"Washington University in St. Louis, St. Louis, MO, USA","institution_ids":["https://openalex.org/I204465549"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080937008","display_name":"Jeremy Buhler","orcid":"https://orcid.org/0000-0002-4159-4226"},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeremy D. Buhler","raw_affiliation_strings":["Washington University in St. Louis, St. Louis, MO, USA"],"affiliations":[{"raw_affiliation_string":"Washington University in St. Louis, St. Louis, MO, USA","institution_ids":["https://openalex.org/I204465549"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006814645","display_name":"Roger D. Chamberlain","orcid":"https://orcid.org/0000-0002-7207-6106"},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Roger D. Chamberlain","raw_affiliation_strings":["Washington University in St. Louis, St. Louis, MO, USA"],"affiliations":[{"raw_affiliation_string":"Washington University in St. Louis, St. Louis, MO, USA","institution_ids":["https://openalex.org/I204465549"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5105839606"],"corresponding_institution_ids":["https://openalex.org/I204465549"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16353474,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"286","last_page":"286"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.769683837890625},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7487010955810547},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6427443623542786},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.610309898853302},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5146759152412415},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5116437077522278},{"id":"https://openalex.org/keywords/space","display_name":"Space (punctuation)","score":0.4978163242340088},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49260836839675903},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.47022509574890137},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.40857261419296265},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3757293224334717},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.36391305923461914},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.32560014724731445},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20570290088653564},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08155322074890137},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07194995880126953}],"concepts":[{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.769683837890625},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7487010955810547},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6427443623542786},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.610309898853302},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5146759152412415},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5116437077522278},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.4978163242340088},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49260836839675903},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.47022509574890137},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40857261419296265},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3757293224334717},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.36391305923461914},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.32560014724731445},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20570290088653564},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08155322074890137},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07194995880126953},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1723112.1723172","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723172","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2619340758","https://openalex.org/W1995613452","https://openalex.org/W2168940796","https://openalex.org/W4282568311","https://openalex.org/W4313484792","https://openalex.org/W2951473296","https://openalex.org/W2883928845","https://openalex.org/W4288420200","https://openalex.org/W3145095675","https://openalex.org/W2024329643"],"abstract_inverted_index":{"Many":[0],"compute-bound":[1],"software":[2],"applications":[3,70],"have":[4],"seen":[5],"order-of-magnitude":[6],"speedups":[7],"using":[8],"application-specific":[9],"accelerators":[10],"built":[11],"on":[12,73],"specialized":[13],"architectures":[14,21],"such":[15],"as":[16,32],"field-programmable":[17],"gate":[18],"arrays.":[19,34],"These":[20],"are":[22],"particularly":[23],"good":[24],"at":[25],"implementing":[26],"systems":[27],"of":[28,48,77,83,101],"recurrence":[29,41],"equations":[30,42],"realized":[31],"systolic":[33],"We":[35,68],"pursue":[36],"high-level":[37],"synthesis":[38],"tools":[39],"for":[40],"that":[43,64,71],"can":[44],"search":[45],"the":[46,97],"space":[47],"possible":[49],"parallel":[50],"array":[51,63],"designs":[52],"to":[53],"optimize":[54],"various":[55],"design":[56],"criteria.":[57],"Most":[58],"existing":[59],"approaches":[60],"produce":[61],"an":[62],"is":[65,96],"latency-space":[66],"optimal.":[67],"target":[69],"operate":[72],"a":[74,81],"large":[75],"collection":[76],"small":[78],"inputs,":[79],"e.g.":[80],"database":[82],"biological":[84],"sequences.":[85],"For":[86],"these":[87],"applications,":[88],"overall":[89],"throughput,":[90],"rather":[91],"than":[92],"latency":[93],"per":[94],"input,":[95],"most":[98],"important":[99],"measure":[100],"performance.":[102]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}