{"id":"https://openalex.org/W2005671831","doi":"https://doi.org/10.1145/1723112.1723152","title":"Degradation in FPGAs","display_name":"Degradation in FPGAs","publication_year":2010,"publication_date":"2010-02-21","ids":{"openalex":"https://openalex.org/W2005671831","doi":"https://doi.org/10.1145/1723112.1723152","mag":"2005671831"},"language":"en","primary_location":{"id":"doi:10.1145/1723112.1723152","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067488586","display_name":"Edward Stott","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Edward A. Stott","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Justin S.J. Wong","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y.K. Cheung","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5067488586"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":8.9479,"has_fulltext":false,"cited_by_count":98,"citation_normalized_percentile":{"value":0.98072186,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"229","last_page":"238"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/degradation","display_name":"Degradation (telecommunications)","score":0.8759818077087402},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7354466319084167},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.7354114055633545},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7276597619056702},{"id":"https://openalex.org/keywords/circuit-reliability","display_name":"Circuit reliability","score":0.6201883554458618},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5924952626228333},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5134530663490295},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.5039300322532654},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45017290115356445},{"id":"https://openalex.org/keywords/negative-bias-temperature-instability","display_name":"Negative-bias temperature instability","score":0.4423424303531647},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34292665123939514},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1801317036151886},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.16081494092941284},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15753763914108276},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11622866988182068},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.10630518198013306},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.08919376134872437},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08230236172676086}],"concepts":[{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.8759818077087402},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7354466319084167},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.7354114055633545},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7276597619056702},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.6201883554458618},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5924952626228333},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5134530663490295},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5039300322532654},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45017290115356445},{"id":"https://openalex.org/C557185","wikidata":"https://www.wikidata.org/wiki/Q6987194","display_name":"Negative-bias temperature instability","level":5,"score":0.4423424303531647},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34292665123939514},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1801317036151886},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.16081494092941284},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15753763914108276},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11622866988182068},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.10630518198013306},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.08919376134872437},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08230236172676086},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1723112.1723152","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5600000023841858,"display_name":"Responsible consumption and production","id":"https://metadata.un.org/sdg/12"}],"awards":[{"id":"https://openalex.org/G3502913390","display_name":null,"funder_award_id":"EP/H013784/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1943183861","https://openalex.org/W1973860191","https://openalex.org/W1979006344","https://openalex.org/W2069345435","https://openalex.org/W2083471150","https://openalex.org/W2096995644","https://openalex.org/W2150056343","https://openalex.org/W2150629048","https://openalex.org/W2154446814","https://openalex.org/W4249918750"],"related_works":["https://openalex.org/W1970920853","https://openalex.org/W2099679924","https://openalex.org/W2738622559","https://openalex.org/W1977755957","https://openalex.org/W2115165828","https://openalex.org/W2126834173","https://openalex.org/W2142908374","https://openalex.org/W1982822282","https://openalex.org/W2076372184","https://openalex.org/W2068470721"],"abstract_inverted_index":{"Progress":[0],"in":[1,64,87,124,137],"VLSI":[2,108],"technology":[3],"is":[4],"driven":[5],"by":[6,131],"increasing":[7,19],"circuit":[8,142],"density":[9],"through":[10],"process":[11],"scaling,":[12],"but":[13],"with":[14],"shrinking":[15],"geometry":[16],"comes":[17],"an":[18,65,73],"threat":[20],"to":[21,27,33,39,45,71],"reliability.":[22],"FPGAs":[23],"are":[24],"uniquely":[25],"placed":[26],"tackle":[28],"degradation":[29,63,86,109,123],"and":[30,37,61,69,99,135],"faults":[31],"due":[32],"their":[34],"regular":[35],"structure":[36],"ability":[38],"reconfigure,":[40],"giving":[41],"them":[42],"the":[43,52,55,92,105,139],"potential":[44],"implement":[46],"system-level":[47],"reliability":[48],"enhancements.":[49],"To":[50],"assess":[51],"scale":[53],"of":[54,95,104],"challenge,":[56],"a":[57,78,83,125],"method":[58],"for":[59],"measuring":[60],"monitoring":[62],"FPGA":[66],"was":[67,116],"developed":[68],"used":[70],"conduct":[72],"accelerated":[74],"life":[75],"test":[76],"on":[77,141],"modern":[79],"device.":[80],"This":[81],"revealed":[82],"clear,":[84],"gradual":[85],"timing":[88],"performance":[89],"that":[90],"matches":[91],"expected":[93],"effects":[94,140],"Negative-Bias":[96],"Temperature":[97],"Instability":[98],"Hot":[100],"Carrier":[101],"Injection,":[102],"two":[103],"most":[106],"important":[107],"mechanisms.":[110],"Further":[111],"insight":[112],"into":[113],"ageing":[114],"phenomena":[115],"gained":[117],"using":[118],"modelling":[119],"--":[120],"showing":[121],"how":[122],"typical":[126],"LUT":[127],"would":[128],"be":[129],"affected":[130],"different":[132],"usage":[133],"conditions,":[134],"predicting":[136],"detail":[138],"behaviour.":[143]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":7},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":9},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":12},{"year":2015,"cited_by_count":10},{"year":2014,"cited_by_count":12},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":8}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}