{"id":"https://openalex.org/W4243872270","doi":"https://doi.org/10.1145/1723112.1723116","title":"Intel nehalem processor core made FPGA synthesizable","display_name":"Intel nehalem processor core made FPGA synthesizable","publication_year":2010,"publication_date":"2010-02-21","ids":{"openalex":"https://openalex.org/W4243872270","doi":"https://doi.org/10.1145/1723112.1723116"},"language":"en","primary_location":{"id":"doi:10.1145/1723112.1723116","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723116","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012238748","display_name":"Graham Schelle","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Graham Schelle","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005994838","display_name":"Jamison D. Collins","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jamison Collins","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014543355","display_name":"Ethan Schuchman","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ethan Schuchman","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066956098","display_name":"Perrry Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Perrry Wang","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101688348","display_name":"Xiang Zou","orcid":"https://orcid.org/0000-0003-0877-8899"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiang Zou","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019370884","display_name":"Gautham N. Chinya","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gautham Chinya","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008524503","display_name":"Ralf Plate","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ralf Plate","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083893712","display_name":"Thorsten Mattner","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Thorsten Mattner","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018163040","display_name":"Franz Olbrich","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Franz Olbrich","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005613664","display_name":"Per Hammarlund","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Per Hammarlund","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018507883","display_name":"Ronak Singhal","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ronak Singhal","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048105007","display_name":"Jim Brayton","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jim Brayton","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017225851","display_name":"Sebastian Steibl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sebastian Steibl","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100371015","display_name":"Hong Wang","orcid":"https://orcid.org/0009-0008-2874-2168"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hong Wang","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":14,"corresponding_author_ids":["https://openalex.org/A5012238748"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":3.4956,"has_fulltext":false,"cited_by_count":49,"citation_normalized_percentile":{"value":0.93456683,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"3","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8339911103248596},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7108657360076904},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.6676874160766602},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6241595149040222},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6113047003746033},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5579767823219299},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.5428159236907959},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4308941662311554},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3354492783546448},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2185196578502655},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.10973772406578064}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8339911103248596},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7108657360076904},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.6676874160766602},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6241595149040222},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6113047003746033},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5579767823219299},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.5428159236907959},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4308941662311554},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3354492783546448},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2185196578502655},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.10973772406578064},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1723112.1723116","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1723112.1723116","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1999777350","https://openalex.org/W2022807575","https://openalex.org/W2030959856","https://openalex.org/W2059817063","https://openalex.org/W2109907925","https://openalex.org/W2140781161","https://openalex.org/W2148658001","https://openalex.org/W2151181453"],"related_works":["https://openalex.org/W2170071008","https://openalex.org/W2103996454","https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W3029775214","https://openalex.org/W2348562861","https://openalex.org/W2170552397","https://openalex.org/W2390650884","https://openalex.org/W2093057572","https://openalex.org/W2129151116"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,16,35,65,70,77],"FPGA-synthesizable":[3],"version":[4],"of":[5,21,50],"the":[6,32,41,55,73,107,117,124],"Intel":[7,56],"Nehalem":[8,74,131],"processor":[9],"core,":[10],"synthesized,":[11],"partitioned":[12],"and":[13,24,48,88,122,138],"mapped":[14],"to":[15,135],"multi-FPGA":[17],"emulation":[18],"system":[19],"consisting":[20],"Xilinx":[22,67],"Virtex-4":[23],"Virtex-5":[25,68],"FPGAs.":[26],"To":[27],"our":[28],"knowledge,":[29],"this":[30],"is":[31,44,76,133],"first":[33],"time":[34],"modern":[36],"state-of-the-art":[37],"x86":[38,141],"design":[39,80,118],"with":[40,81,110,143],"out-of-order":[42],"micro-architecture":[43],"made":[45,61],"FPGA":[46,62,97],"synthesizable":[47,63,109,130],"capable":[49],"high-speed":[51],"cycle-accurate":[52],"emulation.":[53],"Unlike":[54],"Atom":[57],"core":[58,75,125,132],"which":[59],"was":[60],"on":[64],"single":[66],"in":[69,96,105],"previous":[71],"endeavor,":[72],"more":[78],"complex":[79],"aggressive":[82],"clock-gating,":[83],"double":[84],"phase":[85],"latch":[86],"RAMs,":[87],"RTL":[89,108,113],"constructs":[90],"that":[91],"have":[92],"no":[93],"true":[94],"equivalent":[95],"architectures.":[98],"Despite":[99],"these":[100],"challenges,":[101],"we":[102],"are":[103],"successful":[104],"making":[106],"only":[111],"5%":[112],"code":[114],"modifications,":[115],"partitioning":[116],"across":[119],"five":[120],"FPGAs,":[121],"emulating":[123],"at":[126],"520":[127],"KHz.":[128],"The":[129],"able":[134],"boot":[136],"Linux":[137],"execute":[139],"standard":[140],"workloads":[142],"all":[144],"architectural":[145],"features":[146],"enabled.":[147]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}