{"id":"https://openalex.org/W2100300233","doi":"https://doi.org/10.1145/1687399.1687500","title":"Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs","display_name":"Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs","publication_year":2009,"publication_date":"2009-11-02","ids":{"openalex":"https://openalex.org/W2100300233","doi":"https://doi.org/10.1145/1687399.1687500","mag":"2100300233"},"language":"en","primary_location":{"id":"doi:10.1145/1687399.1687500","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1687399.1687500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087709371","display_name":"Yu-Shih Su","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Shih Su","raw_affiliation_strings":["Industrial Technology Research Institute, HsinChu, Taiwan","Industrial Technology Research Institute, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Industrial Technology Research Institute, HsinChu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]},{"raw_affiliation_string":"Industrial Technology Research Institute, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013112058","display_name":"Wing-Kai Hon","orcid":"https://orcid.org/0000-0002-0570-2904"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wing-Kai Hon","raw_affiliation_strings":["National Tsing-Hua University, HsinChu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing-Hua University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111882753","display_name":"Cheng-Chih Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-Chih Yang","raw_affiliation_strings":["National Tsing-Hua University, HsinChu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing-Hua University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102148020","display_name":"Shih-Chieh Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Chieh Chang","raw_affiliation_strings":["National Tsing-Hua University, HsinChu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing-Hua University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105618317","display_name":"Yeong-Jar Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210112000","display_name":"Faraday Technology (Taiwan)","ror":"https://ror.org/021wyrx76","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210112000"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yeong-Jar Chang","raw_affiliation_strings":["Faraday Technology Corporation, HsinChu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faraday Technology Corporation, HsinChu, Taiwan","institution_ids":["https://openalex.org/I4210112000"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":35,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"535","last_page":"538"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7279850840568542},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7013810276985168},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.669404923915863},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.539065420627594},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.522392988204956},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5105782151222229},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5033323168754578},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.49938344955444336},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4583307206630707},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.45729056000709534},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36341190338134766},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.20493286848068237},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15896275639533997},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12589311599731445},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12207308411598206},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1084037721157074}],"concepts":[{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7279850840568542},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7013810276985168},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.669404923915863},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.539065420627594},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.522392988204956},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5105782151222229},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5033323168754578},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.49938344955444336},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4583307206630707},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.45729056000709534},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36341190338134766},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.20493286848068237},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15896275639533997},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12589311599731445},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12207308411598206},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1084037721157074},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1687399.1687500","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1687399.1687500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1976809982","https://openalex.org/W1992904457","https://openalex.org/W2110697119","https://openalex.org/W2125187803","https://openalex.org/W2133916137","https://openalex.org/W2138548848","https://openalex.org/W2142850552","https://openalex.org/W2145293181","https://openalex.org/W2149864516","https://openalex.org/W2155621287","https://openalex.org/W2160653894","https://openalex.org/W2174801549","https://openalex.org/W4243756995"],"related_works":["https://openalex.org/W2116259070","https://openalex.org/W2116514610","https://openalex.org/W2003180247","https://openalex.org/W3201048403","https://openalex.org/W2123512677","https://openalex.org/W2144282137","https://openalex.org/W2891365107","https://openalex.org/W4327499872","https://openalex.org/W4232019485","https://openalex.org/W2032549010"],"abstract_inverted_index":{"In":[0,37],"synchronous":[1],"circuit":[2],"designs,":[3],"clock":[4,17,55],"skew":[5,56,86],"is":[6,87],"difficult":[7],"to":[8,53,100,113],"minimize":[9,54],"because":[10],"a":[11,16,24,73],"single":[12],"physical":[13],"layout":[14],"of":[15,65,81],"tree":[18],"must":[19],"satisfy":[20],"multiple":[21],"constraints":[22],"in":[23],"complicated":[25],"power":[26,59],"mode":[27],"environment":[28],"where":[29],"certain":[30],"modules":[31],"may":[32],"operate":[33],"with":[34],"different":[35,58],"voltages.":[36],"this":[38],"paper,":[39],"we":[40,71],"use":[41],"Adjustable":[42],"Delay":[43],"Buffers":[44],"(ADB)":[45],"whose":[46],"delays":[47],"can":[48],"be":[49],"tuned":[50],"or":[51],"adjusted":[52],"under":[57],"modes.":[60],"Assuming":[61],"that":[62,84],"the":[63,79,85],"positions":[64,103],"k":[66],"ADBs":[67,82],"are":[68],"already":[69],"determined,":[70],"propose":[72,96],"linear-time":[74],"optimal":[75,88],"algorithm":[76],"which":[77],"assigns":[78],"values":[80],"so":[83],"among":[89],"all":[90],"possible":[91],"ADB":[92],"assignments.":[93],"We":[94],"also":[95],"an":[97],"efficient":[98],"heuristic":[99],"determine":[101],"good":[102],"for":[104],"ADBs.":[105,116],"Our":[106],"results":[107],"show":[108],"significant":[109],"improvement":[110],"when":[111],"compared":[112],"cases":[114],"without":[115],"Categories":[117],"and":[118],"Subject":[119],"Descriptors":[120],"B.6.3":[121],"[Logic":[122],"Design]:":[123],"Design":[124],"Aids":[125],"\u2014":[126],"Optimization":[127],"General":[128],"Terms:":[129],"Algorithms,":[130],"Reliability":[131]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}