{"id":"https://openalex.org/W2158533859","doi":"https://doi.org/10.1145/1687399.1687401","title":"First steps towards SAT-based formal analog verification","display_name":"First steps towards SAT-based formal analog verification","publication_year":2009,"publication_date":"2009-11-02","ids":{"openalex":"https://openalex.org/W2158533859","doi":"https://doi.org/10.1145/1687399.1687401","mag":"2158533859"},"language":"en","primary_location":{"id":"doi:10.1145/1687399.1687401","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1687399.1687401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043148599","display_name":"Saurabh K Tiwary","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Saurabh K. Tiwary","raw_affiliation_strings":["Cadence Research Labs, Berkeley, CA"],"affiliations":[{"raw_affiliation_string":"Cadence Research Labs, Berkeley, CA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025098067","display_name":"Anubhav Gupta","orcid":"https://orcid.org/0000-0003-0187-8192"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anubhav Gupta","raw_affiliation_strings":["Cadence Research Labs, Berkeley, CA"],"affiliations":[{"raw_affiliation_string":"Cadence Research Labs, Berkeley, CA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060124540","display_name":"Joel Phillips","orcid":"https://orcid.org/0000-0002-3437-425X"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel R. Phillips","raw_affiliation_strings":["Cadence Research Labs, Berkeley, CA"],"affiliations":[{"raw_affiliation_string":"Cadence Research Labs, Berkeley, CA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042435588","display_name":"Claudio Pinello","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Claudio Pinello","raw_affiliation_strings":["Cadence Research Labs, Berkeley, CA"],"affiliations":[{"raw_affiliation_string":"Cadence Research Labs, Berkeley, CA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015236498","display_name":"Radu Zlatanovici","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Radu Zlatanovici","raw_affiliation_strings":["Cadence Research Labs, Berkeley, CA"],"affiliations":[{"raw_affiliation_string":"Cadence Research Labs, Berkeley, CA","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5043148599"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":3.085,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.91896024,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8921014666557312},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7677202820777893},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.7324326038360596},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.6820139288902283},{"id":"https://openalex.org/keywords/satisfiability-modulo-theories","display_name":"Satisfiability modulo theories","score":0.6166589856147766},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.5929131507873535},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.5170153379440308},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5101035237312317},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.48606517910957336},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.47012126445770264},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.44722452759742737},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.4417553246021271},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4285411834716797},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.42523759603500366},{"id":"https://openalex.org/keywords/satisfiability","display_name":"Satisfiability","score":0.41426512598991394},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3712608516216278},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2401251196861267},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1657092571258545},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15525886416435242}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8921014666557312},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7677202820777893},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.7324326038360596},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.6820139288902283},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.6166589856147766},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.5929131507873535},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.5170153379440308},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5101035237312317},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.48606517910957336},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.47012126445770264},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.44722452759742737},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.4417553246021271},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4285411834716797},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.42523759603500366},{"id":"https://openalex.org/C168773769","wikidata":"https://www.wikidata.org/wiki/Q1350299","display_name":"Satisfiability","level":2,"score":0.41426512598991394},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3712608516216278},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2401251196861267},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1657092571258545},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15525886416435242},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1687399.1687401","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1687399.1687401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W203600336","https://openalex.org/W1480537711","https://openalex.org/W1495851026","https://openalex.org/W1499853177","https://openalex.org/W1522694098","https://openalex.org/W1537946603","https://openalex.org/W1905380539","https://openalex.org/W2001859357","https://openalex.org/W2104439088","https://openalex.org/W2124274423","https://openalex.org/W2142091551","https://openalex.org/W2155660165","https://openalex.org/W2493685774","https://openalex.org/W2561675875","https://openalex.org/W3148137902"],"related_works":["https://openalex.org/W21388859","https://openalex.org/W3046927439","https://openalex.org/W2360029815","https://openalex.org/W4295791056","https://openalex.org/W2895905110","https://openalex.org/W2171786655","https://openalex.org/W2788911029","https://openalex.org/W4234123702","https://openalex.org/W2125763413","https://openalex.org/W1971664049"],"abstract_inverted_index":{"Boolean":[0],"satisfiability":[1,30],"(SAT)":[2],"based":[3,79],"methods":[4],"have":[5,120],"traditionally":[6],"been":[7],"popular":[8],"for":[9,13,21,72,102],"formally":[10],"verifying":[11],"properties":[12],"digital":[14],"circuits.":[15],"We":[16,32,98,119,140],"present":[17,100],"a":[18,23,29,35,59,68,125,136],"novel":[19],"methodology":[20],"formulating":[22],"SPICE-type":[24],"circuit":[25,36],"simulation":[26,56,86],"problem":[27,57,61],"as":[28,74,76],"problem.":[31],"start":[33],"with":[34],"level":[37,49],"netlist,":[38],"capture":[39],"the":[40,44,47,55,88,92,111,131,142],"non-linear":[41],"behavior":[42],"of":[43,114,144,154],"circuits":[45],"at":[46,134],"transistor":[48],"via":[50,67],"conservative":[51],"approximations":[52],"and":[53,81,105,164,169],"transform":[54],"into":[58,124],"search":[60],"that":[62,157],"can":[63],"be":[64],"exhaustively":[65],"explored":[66],"SAT":[69],"solver.":[70],"Thus,":[71],"DC":[73],"well":[75],"fixed":[77],"time-step":[78],"transient":[80],"periodic":[82],"steady":[83],"state":[84],"(PSS)":[85],"formulations,":[87],"solutions":[89],"produced":[90],"by":[91,147],"solver":[93],"are":[94],"formal":[95,137],"in":[96],"nature.":[97],"also":[99],"algorithms":[101],"abstraction":[103],"refinement":[104],"smart":[106],"interval":[107],"generation":[108],"to":[109],"improve":[110],"computational":[112],"efficiency":[113],"our":[115,122,145],"proposed":[116],"solution":[117],"scheme.":[118],"implemented":[121],"ideas":[123,146],"tool":[126],"called":[127],"fSpice":[128],"which":[129],"is":[130],"first":[132],"attempt":[133],"building":[135],"SPICE":[138],"engine.":[139],"demonstrate":[141],"applicability":[143],"showing":[148],"experimental":[149],"results":[150],"using":[151],"pruned":[152],"versions":[153],"real":[155],"designs":[156],"faced":[158],"challenges":[159],"during":[160],"chip":[161],"tape-out.":[162],"Categories":[163],"Subject":[165],"Descriptors":[166],"I.6.5":[167],"[Simulation":[168],"Modeling]:":[170],"Model":[171],"Development":[172],"General":[173],"Terms":[174],"Algorithms,":[175],"Design":[176]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
