{"id":"https://openalex.org/W2113109796","doi":"https://doi.org/10.1145/1629911.1630026","title":"A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion","display_name":"A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion","publication_year":2009,"publication_date":"2009-07-26","ids":{"openalex":"https://openalex.org/W2113109796","doi":"https://doi.org/10.1145/1629911.1630026","mag":"2113109796"},"language":"en","primary_location":{"id":"doi:10.1145/1629911.1630026","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629911.1630026","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 46th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031580282","display_name":"Shiyan Hu","orcid":"https://orcid.org/0000-0003-2512-0634"},"institutions":[{"id":"https://openalex.org/I11957088","display_name":"Michigan Technological University","ror":"https://ror.org/0036rpn28","country_code":"US","type":"education","lineage":["https://openalex.org/I11957088"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shiyan Hu","raw_affiliation_strings":["Michigan Technological University, Houghton, Michigan","Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, 49931 USA"],"affiliations":[{"raw_affiliation_string":"Michigan Technological University, Houghton, Michigan","institution_ids":["https://openalex.org/I11957088"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, 49931 USA","institution_ids":["https://openalex.org/I11957088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101528588","display_name":"Zhuo Li","orcid":"https://orcid.org/0009-0009-0631-7977"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhuo Li","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, Texas","IBM Austin Research Laboratory, 11501 Burnet Road, Texas 78758, USA"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, Texas","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratory, 11501 Burnet Road, Texas 78758, USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113656006","display_name":"Charles J. Alpert","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles J. Alpert","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, Texas","IBM Austin Research Laboratory, 11501 Burnet Road, Texas 78758, USA"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, Texas","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratory, 11501 Burnet Road, Texas 78758, USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5031580282"],"corresponding_institution_ids":["https://openalex.org/I11957088"],"apc_list":null,"apc_paid":null,"fwci":1.216,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.81212153,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"424","last_page":"429"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.8034638166427612},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.7042940258979797},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6913001537322998},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6573545932769775},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5790903568267822},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5734477043151855},{"id":"https://openalex.org/keywords/buffer","display_name":"Buffer (optical fiber)","score":0.5086063146591187},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5041810274124146},{"id":"https://openalex.org/keywords/time-complexity","display_name":"Time complexity","score":0.4937377870082855},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4589155614376068},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.45636340975761414},{"id":"https://openalex.org/keywords/dynamic-programming","display_name":"Dynamic programming","score":0.43375590443611145},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.4327622950077057},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.33827030658721924},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.295232892036438},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2515636682510376},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21452230215072632},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17152374982833862},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16504943370819092}],"concepts":[{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.8034638166427612},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.7042940258979797},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6913001537322998},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6573545932769775},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5790903568267822},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5734477043151855},{"id":"https://openalex.org/C145018004","wikidata":"https://www.wikidata.org/wiki/Q4985944","display_name":"Buffer (optical fiber)","level":2,"score":0.5086063146591187},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5041810274124146},{"id":"https://openalex.org/C311688","wikidata":"https://www.wikidata.org/wiki/Q2393193","display_name":"Time complexity","level":2,"score":0.4937377870082855},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4589155614376068},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.45636340975761414},{"id":"https://openalex.org/C37404715","wikidata":"https://www.wikidata.org/wiki/Q380679","display_name":"Dynamic programming","level":2,"score":0.43375590443611145},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.4327622950077057},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.33827030658721924},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.295232892036438},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2515636682510376},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21452230215072632},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17152374982833862},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16504943370819092},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1629911.1630026","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629911.1630026","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 46th Annual Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:digitalcommons.mtu.edu:michigantech-p-31802","is_oa":false,"landing_page_url":"https://digitalcommons.mtu.edu/michigantech-p/12500","pdf_url":null,"source":{"id":"https://openalex.org/S4377196391","display_name":"Digital Commons - Michigan Tech (Michigan Technological University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I11957088","host_organization_name":"Michigan Technological University","host_organization_lineage":["https://openalex.org/I11957088"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Michigan Tech Publications, Part 1","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1607679225","https://openalex.org/W1967474595","https://openalex.org/W1971048398","https://openalex.org/W1997797456","https://openalex.org/W2012173826","https://openalex.org/W2014144678","https://openalex.org/W2049546399","https://openalex.org/W2050219435","https://openalex.org/W2068674204","https://openalex.org/W2069162780","https://openalex.org/W2083404205","https://openalex.org/W2097175306","https://openalex.org/W2102313509","https://openalex.org/W2109138471","https://openalex.org/W2115106074","https://openalex.org/W2123316553","https://openalex.org/W2127434816","https://openalex.org/W2153593246","https://openalex.org/W2160252016","https://openalex.org/W2489328233","https://openalex.org/W4232214728"],"related_works":["https://openalex.org/W2097227107","https://openalex.org/W2366025885","https://openalex.org/W2181385951","https://openalex.org/W1727049600","https://openalex.org/W1481897060","https://openalex.org/W2183812348","https://openalex.org/W4313890168","https://openalex.org/W2358255476","https://openalex.org/W1886723318","https://openalex.org/W4254290183"],"abstract_inverted_index":{"As":[0,17],"VLSI":[1],"technology":[2],"enters":[3],"the":[4,11,14,20,32,54,72],"nanoscale":[5],"regime,":[6],"interconnect":[7,25],"delay":[8],"has":[9],"become":[10],"bottleneck":[12],"of":[13,19,71],"circuit":[15],"timing.":[16],"one":[18,70],"most":[21,73],"powerful":[22],"techniques":[23],"for":[24],"optimization,":[26],"buffer":[27,67],"insertion":[28,68],"is":[29,37,69,81],"indispensable":[30],"in":[31,53,76],"physical":[33,77],"synthesis":[34],"flow.":[35],"Buffering":[36],"known":[38],"to":[39,49],"be":[40],"NP-complete":[41],"and":[42],"existing":[43],"works":[44],"either":[45],"explore":[46],"dynamic":[47],"programming":[48],"compute":[50],"optimal":[51],"solution":[52],"worst-case":[55],"exponential":[56],"time":[57],"or":[58],"design":[59],"efficient":[60,83],"heuristics":[61],"without":[62],"performance":[63,88],"guarantee.":[64],"Even":[65],"if":[66],"studied":[74],"problems":[75],"design,":[78],"whether":[79],"there":[80],"an":[82],"algorithm":[84],"with":[85],"provably":[86],"good":[87],"still":[89],"remains":[90],"unknown.":[91]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
