{"id":"https://openalex.org/W2169605615","doi":"https://doi.org/10.1145/1629911.1629974","title":"MPTLsim","display_name":"MPTLsim","publication_year":2009,"publication_date":"2009-07-26","ids":{"openalex":"https://openalex.org/W2169605615","doi":"https://doi.org/10.1145/1629911.1629974","mag":"2169605615"},"language":"en","primary_location":{"id":"doi:10.1145/1629911.1629974","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629911.1629974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 46th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062711128","display_name":"Hui Zeng","orcid":"https://orcid.org/0000-0002-7657-6714"},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hui Zeng","raw_affiliation_strings":["State University of New York, Binghamton, NY"],"affiliations":[{"raw_affiliation_string":"State University of New York, Binghamton, NY","institution_ids":["https://openalex.org/I123946342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067918343","display_name":"Matt T. Yourst","orcid":null},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matt Yourst","raw_affiliation_strings":["State University of New York, Binghamton, NY"],"affiliations":[{"raw_affiliation_string":"State University of New York, Binghamton, NY","institution_ids":["https://openalex.org/I123946342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043921638","display_name":"Kanad Ghose","orcid":"https://orcid.org/0000-0002-5509-6543"},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kanad Ghose","raw_affiliation_strings":["State University of New York, Binghamton, NY"],"affiliations":[{"raw_affiliation_string":"State University of New York, Binghamton, NY","institution_ids":["https://openalex.org/I123946342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101850696","display_name":"Dmitry Ponomarev","orcid":"https://orcid.org/0000-0002-7776-3933"},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dmitry Ponomarev","raw_affiliation_strings":["State University of New York, Binghamton, NY"],"affiliations":[{"raw_affiliation_string":"State University of New York, Binghamton, NY","institution_ids":["https://openalex.org/I123946342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5062711128"],"corresponding_institution_ids":["https://openalex.org/I123946342"],"apc_list":null,"apc_paid":null,"fwci":1.3191,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.82585101,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"226","last_page":"231"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.9023222923278809},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8436110019683838},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.806930661201477},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.634841799736023},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5681822896003723},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5104583501815796},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49015507102012634},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4747474789619446},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.46235617995262146},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4499158561229706},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2984372675418854},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2853737473487854},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.2751694917678833},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.15684908628463745},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.10784241557121277},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.09445276856422424}],"concepts":[{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.9023222923278809},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8436110019683838},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.806930661201477},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.634841799736023},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5681822896003723},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5104583501815796},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49015507102012634},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4747474789619446},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.46235617995262146},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4499158561229706},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2984372675418854},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2853737473487854},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2751694917678833},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.15684908628463745},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.10784241557121277},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.09445276856422424}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1629911.1629974","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629911.1629974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 46th Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2115215475","display_name":null,"funder_award_id":"CNS-072081CNS-0454298","funder_id":"https://openalex.org/F4320307102","funder_display_name":"Intel Corporation"}],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1850405760","https://openalex.org/W1990800384","https://openalex.org/W2044206819","https://openalex.org/W2096864363","https://openalex.org/W2097117297","https://openalex.org/W2104225326","https://openalex.org/W2113167168","https://openalex.org/W2118532220","https://openalex.org/W2120635877","https://openalex.org/W2134633067","https://openalex.org/W2140057257","https://openalex.org/W2149239353","https://openalex.org/W2156858199","https://openalex.org/W2164264749","https://openalex.org/W4239035626","https://openalex.org/W4239813889"],"related_works":["https://openalex.org/W2516517078","https://openalex.org/W1980322368","https://openalex.org/W3012895752","https://openalex.org/W2096357811","https://openalex.org/W2150909864","https://openalex.org/W4382618825","https://openalex.org/W2161286015","https://openalex.org/W4386903460","https://openalex.org/W2900372418","https://openalex.org/W2741067476"],"abstract_inverted_index":{"Current":[0],"microprocessors":[1],"are":[2],"effectively":[3],"a":[4,20,40,104,108],"system-on-a-chip,":[5],"as":[6,61,63,92],"they":[7],"incorporate":[8],"processing":[9],"cores,":[10],"interconnections,":[11,96],"shared":[12],"and":[13,16,30,46,67,80,85,99],"private":[14],"caches":[15],"DRAM":[17,65],"controllers":[18],"on":[19],"single":[21],"die.":[22],"Consequently,":[23],"it":[24],"is":[25],"imperative":[26],"to":[27],"have":[28],"fast":[29],"accurate":[31],"simulation":[32,79,87],"tools":[33],"for":[34,42,75],"such":[35,39,91],"systems;":[36],"this":[37],"paper":[38],"tool":[41],"simulating":[43],"all":[44],"current":[45],"announced":[47],"variants":[48],"of":[49,88],"multicore":[50],"processors":[51],"that":[52],"use":[53],"the":[54,71,78,82,86],"predominant":[55],"PC":[56],"(X86,":[57],"X86-64)":[58],"instruction":[59],"set,":[60],"well":[62],"external":[64],"memory":[66,97],"buses.":[68],"We":[69,101],"discuss":[70],"major":[72],"techniques":[73],"used":[74],"speeding":[76],"up":[77],"improving":[81],"overall":[83],"accuracy,":[84],"system-level":[89],"details":[90],"coherent":[93],"caches,":[94],"on-chip":[95],"bus":[98],"DRAM.":[100],"also":[102],"demonstrate":[103],"8-fold":[105],"speedup":[106],"against":[107],"widely-used":[109],"popular":[110],"tool.":[111]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}