{"id":"https://openalex.org/W2147793571","doi":"https://doi.org/10.1145/1629911.1629942","title":"Device/circuit interactions at 22nm technology node","display_name":"Device/circuit interactions at 22nm technology node","publication_year":2009,"publication_date":"2009-07-26","ids":{"openalex":"https://openalex.org/W2147793571","doi":"https://doi.org/10.1145/1629911.1629942","mag":"2147793571"},"language":"en","primary_location":{"id":"doi:10.1145/1629911.1629942","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629911.1629942","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 46th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003048953","display_name":"Jaydeep P. Kulkarni","orcid":"https://orcid.org/0000-0002-0258-6776"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaydeep P. Kulkarni","raw_affiliation_strings":["Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044276472","display_name":"Sumeet Kumar Gupta","orcid":"https://orcid.org/0000-0001-5609-9722"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sumeet Kumar Gupta","raw_affiliation_strings":["Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5031161187"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":2.0935,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.87997251,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"97","last_page":"102"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.7248423099517822},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6790600419044495},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.646717369556427},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5566231608390808},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5225824117660522},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4833216667175293},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.47181665897369385},{"id":"https://openalex.org/keywords/design-technology","display_name":"Design technology","score":0.468352735042572},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45633310079574585},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4491160809993744},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.43518760800361633},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42045503854751587},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3967728018760681},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2493547797203064},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2132115662097931},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.1927097737789154}],"concepts":[{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.7248423099517822},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6790600419044495},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.646717369556427},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5566231608390808},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5225824117660522},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4833216667175293},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.47181665897369385},{"id":"https://openalex.org/C179737136","wikidata":"https://www.wikidata.org/wiki/Q5264382","display_name":"Design technology","level":2,"score":0.468352735042572},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45633310079574585},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4491160809993744},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.43518760800361633},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42045503854751587},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3967728018760681},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2493547797203064},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2132115662097931},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.1927097737789154},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1629911.1629942","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629911.1629942","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 46th Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2042536271","https://openalex.org/W2067168777","https://openalex.org/W2095596186","https://openalex.org/W2104677471","https://openalex.org/W2105470988","https://openalex.org/W2112475735","https://openalex.org/W2135818056","https://openalex.org/W2136103183","https://openalex.org/W2150952982","https://openalex.org/W2155118152","https://openalex.org/W2156713962","https://openalex.org/W2160580687","https://openalex.org/W2161954730"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2766377030","https://openalex.org/W2041787842"],"abstract_inverted_index":{"As":[0],"transition":[1],"is":[2,32,99],"being":[3,19],"made":[4],"into":[5],"22nm":[6],"node,":[7],"technology":[8,36,48],"considerations":[9],"and":[10,24,39,47,69,93],"device":[11,45,87],"architectures":[12],"suitable":[13],"for":[14,35,89,112],"such":[15,113],"scaled":[16,27,114],"technologies":[17],"are":[18],"explored.":[20],"To":[21],"design":[22,41,52,63,76,95,110],"circuits":[23],"systems":[25],"at":[26,64,72],"nodes,":[28],"we":[29,57,84,103],"believe":[30],"there":[31],"a":[33],"need":[34],"aware":[37],"circuit":[38],"system":[40,109],"methodology":[42],"that":[43],"considers":[44],"architecture,":[46],"challenges":[49,60],"to":[50,78],"achieve":[51],"optimality.":[53],"In":[54,82],"this":[55],"paper,":[56],"discuss":[58,85,105],"the":[59,65],"of":[61,75],"device-circuit-system":[62],"22":[66],"nm":[67],"node":[68],"present":[70],"techniques":[71],"different":[73,86],"levels":[74],"abstraction":[77],"meet":[79],"these":[80],"challenges.":[81],"particular,":[83],"options":[88],"multi-gate":[90,97],"FETs.":[91],"Logic":[92],"memory":[94],"using":[96],"FETs":[98],"also":[100],"considered.":[101],"Finally,":[102],"briefly":[104],"process":[106],"variation":[107],"tolerant":[108],"methodologies":[111],"technologies.":[115]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
