{"id":"https://openalex.org/W1992332857","doi":"https://doi.org/10.1145/1629435.1629500","title":"Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip","display_name":"Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip","publication_year":2009,"publication_date":"2009-10-11","ids":{"openalex":"https://openalex.org/W1992332857","doi":"https://doi.org/10.1145/1629435.1629500","mag":"1992332857"},"language":"en","primary_location":{"id":"doi:10.1145/1629435.1629500","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629435.1629500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089675008","display_name":"Matthias Bo Stuart","orcid":"https://orcid.org/0000-0003-0809-530X"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Matthias Bo Stuart","raw_affiliation_strings":["Technical University of Denmark, Lyngby, Denmark","Technical University of Denmark,,,Lyngby,,Denmark"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Denmark, Lyngby, Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"Technical University of Denmark,,,Lyngby,,Denmark","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008216353","display_name":"Mikkel Bystrup Stensgaard","orcid":null},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Mikkel Bystrup Stensgaard","raw_affiliation_strings":["Technical University of Denmark, Lyngby, Denmark","Technical University of Denmark,,,Lyngby,,Denmark"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Denmark, Lyngby, Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"Technical University of Denmark,,,Lyngby,,Denmark","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055051850","display_name":"Jens Spars\u00f8","orcid":"https://orcid.org/0000-0002-0961-9438"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Jens Spars\u00f8","raw_affiliation_strings":["Technical University of Denmark, Lyngby, Denmark","Technical University of Denmark,,,Lyngby,,Denmark"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Denmark, Lyngby, Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"Technical University of Denmark,,,Lyngby,,Denmark","institution_ids":["https://openalex.org/I96673099"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I96673099"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"481","last_page":"490"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9857000112533569,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.720618486404419},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6564074754714966},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6466796398162842},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.615634560585022},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.5983358025550842},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5806035399436951},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5559322834014893},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5480376482009888},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.497116357088089},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47581201791763306},{"id":"https://openalex.org/keywords/packet-switching","display_name":"Packet switching","score":0.4700288474559784},{"id":"https://openalex.org/keywords/circuit-switching","display_name":"Circuit switching","score":0.4329336881637573},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.42247578501701355},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4206463098526001},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.40564507246017456},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.35444551706314087},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20320478081703186},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11115851998329163},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10494616627693176}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.720618486404419},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6564074754714966},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6466796398162842},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.615634560585022},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.5983358025550842},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5806035399436951},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5559322834014893},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5480376482009888},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.497116357088089},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47581201791763306},{"id":"https://openalex.org/C113508815","wikidata":"https://www.wikidata.org/wiki/Q193446","display_name":"Packet switching","level":3,"score":0.4700288474559784},{"id":"https://openalex.org/C74294265","wikidata":"https://www.wikidata.org/wiki/Q506273","display_name":"Circuit switching","level":2,"score":0.4329336881637573},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.42247578501701355},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4206463098526001},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.40564507246017456},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.35444551706314087},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20320478081703186},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11115851998329163},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10494616627693176}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1629435.1629500","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629435.1629500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:publications/18f35ed0-c8c9-46e3-8174-461f0fb4363c","is_oa":false,"landing_page_url":"https://orbit.dtu.dk/en/publications/18f35ed0-c8c9-46e3-8174-461f0fb4363c","pdf_url":null,"source":{"id":"https://openalex.org/S4306400705","display_name":"Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I96673099","host_organization_name":"Technical University of Denmark","host_organization_lineage":["https://openalex.org/I96673099"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Stuart , M B , Stensgaard , M B & Spars\u00f8 , J 2009 , Synthesis of Topology Configurations and Deadlock Free Routing Algorithms for ReNoC-based Systems-on-Chip . in International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) . 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis , Grenoble , France , 11/10/2009 .","raw_type":"contributionToPeriodical"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1999823427","https://openalex.org/W2008041840","https://openalex.org/W2022673945","https://openalex.org/W2104603273","https://openalex.org/W2118597853","https://openalex.org/W2118961575","https://openalex.org/W2123184444","https://openalex.org/W2126349935","https://openalex.org/W2130512670","https://openalex.org/W2132249049","https://openalex.org/W2133953582","https://openalex.org/W2139356019","https://openalex.org/W2154689056","https://openalex.org/W2156954907","https://openalex.org/W2167160754","https://openalex.org/W2168082067"],"related_works":["https://openalex.org/W2169595109","https://openalex.org/W2010120844","https://openalex.org/W8314501","https://openalex.org/W2138676945","https://openalex.org/W640242547","https://openalex.org/W2006278052","https://openalex.org/W2112772280","https://openalex.org/W2163594390","https://openalex.org/W4238242975","https://openalex.org/W2012652058"],"abstract_inverted_index":{"In":[0],"the":[1],"near":[2],"future,":[3],"generic":[4,15],"System-on-Chip":[5],"(SoC)":[6],"platforms":[7,16],"will":[8],"be":[9,44],"replacing":[10],"custom":[11],"designed":[12],"SoCs.":[13],"Such":[14],"require":[17],"a":[18,26,49,56],"highly":[19],"flexible":[20],"interconnect":[21],"in":[22],"order":[23],"to":[24,43],"support":[25],"wide":[27],"variety":[28],"of":[29,48,58],"applications.":[30],"The":[31],"ReNoC":[32],"architecture":[33,54],"provides":[34],"this":[35],"by":[36],"allowing":[37],"power":[38],"efficient,":[39],"application":[40],"specific":[41],"topologies":[42],"configured":[45],"on":[46],"top":[47],"fixed":[50],"but":[51],"reconfigurable":[52],"physical":[53,62],"through":[55],"mixture":[57],"packet":[59],"switching":[60],"and":[61],"circuit":[63],"switching.":[64]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}