{"id":"https://openalex.org/W2052831356","doi":"https://doi.org/10.1145/1629435.1629482","title":"Supporting RTL flow compatibility in a microarchitecture-level design framework","display_name":"Supporting RTL flow compatibility in a microarchitecture-level design framework","publication_year":2009,"publication_date":"2009-10-11","ids":{"openalex":"https://openalex.org/W2052831356","doi":"https://doi.org/10.1145/1629435.1629482","mag":"2052831356"},"language":"en","primary_location":{"id":"doi:10.1145/1629435.1629482","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629435.1629482","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022049158","display_name":"Daniel Schwartz\u2010Narbonne","orcid":"https://orcid.org/0000-0002-0453-2552"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Daniel Schwartz-Narbonne","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA","Princeton University , Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University , Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000546537","display_name":"Carven Chan","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carven Chan","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA","Princeton University , Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University , Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103192187","display_name":"Yogesh S. Mahajan","orcid":"https://orcid.org/0000-0002-6658-602X"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yogesh Mahajan","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA","Princeton University , Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University , Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085975362","display_name":"Sharad Malik","orcid":"https://orcid.org/0000-0002-0837-5443"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sharad Malik","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA","Princeton University , Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University , Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5022049158"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":0.34342244,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.6745914,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"343","last_page":"352"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.989799976348877,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8211653232574463},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6938022375106812},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.6768923401832581},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6477166414260864},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6158604025840759},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5478007197380066},{"id":"https://openalex.org/keywords/semantics","display_name":"Semantics (computer science)","score":0.4888257384300232},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48713037371635437},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.45488905906677246},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.4474058151245117},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4380134046077728},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.431461364030838},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42714303731918335},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3315480351448059},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.23438438773155212},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.1683104932308197},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.07676610350608826}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8211653232574463},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6938022375106812},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.6768923401832581},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6477166414260864},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6158604025840759},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5478007197380066},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.4888257384300232},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48713037371635437},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.45488905906677246},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.4474058151245117},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4380134046077728},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.431461364030838},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42714303731918335},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3315480351448059},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.23438438773155212},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.1683104932308197},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.07676610350608826}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1629435.1629482","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1629435.1629482","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5699999928474426,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1555915743","https://openalex.org/W1556078275","https://openalex.org/W2006570958","https://openalex.org/W2016346377","https://openalex.org/W2043132803","https://openalex.org/W2097191929","https://openalex.org/W2097331811","https://openalex.org/W2109589569","https://openalex.org/W2120665166","https://openalex.org/W2121163444","https://openalex.org/W2122107861","https://openalex.org/W2130088511","https://openalex.org/W2156088664","https://openalex.org/W2158391679","https://openalex.org/W2214578075","https://openalex.org/W4241706643","https://openalex.org/W4256238177"],"related_works":["https://openalex.org/W3002976045","https://openalex.org/W2269990635","https://openalex.org/W4247178515","https://openalex.org/W2543290882","https://openalex.org/W1981284526","https://openalex.org/W2097236935","https://openalex.org/W2129507101","https://openalex.org/W2295153704","https://openalex.org/W3013057549","https://openalex.org/W3168383044"],"abstract_inverted_index":{"Current":[0],"RTL-based":[1],"design":[2,68],"methodologies":[3],"face":[4],"significant":[5],"scaling":[6],"challenges":[7],"related":[8],"to":[9,35,95],"the":[10,26,30,36,52,105,109,112,122,126,147,150],"difficulty":[11],"of":[12,51,55,108,114,121,128],"designing,":[13],"modifying,":[14],"and":[15,136,144],"verifying":[16,119],"RTL.":[17],"RTL":[18,102],"contains":[19],"primarily":[20],"low":[21],"level":[22,67],"structural":[23],"information":[24],"about":[25],"design.":[27,47,139],"In":[28,73],"contrast,":[29],"microarchitecture-level":[31],"is":[32,57],"much":[33],"closer":[34],"specification":[37],"level,":[38],"making":[39],"it":[40,88],"an":[41],"effective":[42],"entry":[43],"point":[44],"for":[45,60,65,98,117],"hardware":[46],"The":[48],"explicit":[49],"description":[50],"high-level":[53],"units":[54],"work":[56],"also":[58],"beneficial":[59],"verification.":[61],"Currently":[62],"used":[63],"models":[64],"high":[66],"have":[69],"very":[70],"complex":[71],"semantics.":[72,84],"this":[74,129],"paper,":[75],"we":[76],"present":[77],"a":[78,91,137],"microarchitectural":[79],"modeling":[80],"language":[81],"with":[82,100],"simpler":[83,93],"We":[85,124,140],"demonstrate":[86,125],"that":[87],"results":[89],"in":[90],"significantly":[92],"synthesis":[94,148],"Verilog,":[96],"providing":[97],"integration":[99],"existing":[101],"flows.":[103],"Moreover,":[104],"simple":[106],"semantics":[107],"model":[110],"enable":[111],"generation":[113],"PSL":[115],"assertions":[116],"functionally":[118],"correctness":[120],"synthesis.":[123],"efficacy":[127],"approach":[130],"through":[131],"two":[132],"case-studies---a":[133],"router":[134],"switch":[135],"processor":[138],"synthesized":[141],"both":[142],"designs,":[143],"formally":[145],"verified":[146],"using":[149],"generated":[151],"assertions.":[152]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}