{"id":"https://openalex.org/W2021388492","doi":"https://doi.org/10.1145/1594233.1594306","title":"Exploration of 3D stacked L2 cache design for high performance and efficient thermal control","display_name":"Exploration of 3D stacked L2 cache design for high performance and efficient thermal control","publication_year":2009,"publication_date":"2009-08-19","ids":{"openalex":"https://openalex.org/W2021388492","doi":"https://doi.org/10.1145/1594233.1594306","mag":"2021388492"},"language":"en","primary_location":{"id":"doi:10.1145/1594233.1594306","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1594233.1594306","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101850376","display_name":"Guangyu Sun","orcid":"https://orcid.org/0000-0001-6436-0820"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Guangyu Sun","raw_affiliation_strings":["Pennsylvania State University, State College, PA, USA","Pennsylvania State University, State College, PA., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University, State College, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Pennsylvania State University, State College, PA., USA#TAB#","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100837627","display_name":"Xiaoxia Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaoxia Wu","raw_affiliation_strings":["Pennsylvania State University, State College, PA, USA","Pennsylvania State University, State College, PA., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University, State College, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Pennsylvania State University, State College, PA., USA#TAB#","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100385336","display_name":"Yuan Xie","orcid":"https://orcid.org/0000-0003-2093-1788"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuan Xie","raw_affiliation_strings":["Pennsylvania State University, State College, PA, USA","Pennsylvania State University, State College, PA., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University, State College, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Pennsylvania State University, State College, PA., USA#TAB#","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101850376"],"corresponding_institution_ids":["https://openalex.org/I130769515"],"apc_list":null,"apc_paid":null,"fwci":3.1659,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.9201776,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"295","last_page":"298"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7851243019104004},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7106163501739502},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5394870042800903},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.46149882674217224},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.44990476965904236},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4467589259147644},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.4354532063007355},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.42955416440963745},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.42891374230384827},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3624216318130493},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3527355194091797},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33237749338150024},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1532439887523651},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15243777632713318}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7851243019104004},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7106163501739502},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5394870042800903},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.46149882674217224},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.44990476965904236},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4467589259147644},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.4354532063007355},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.42955416440963745},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.42891374230384827},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3624216318130493},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3527355194091797},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33237749338150024},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1532439887523651},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15243777632713318},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1594233.1594306","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1594233.1594306","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1987131925","https://openalex.org/W2100335359","https://openalex.org/W2101181484","https://openalex.org/W2101308451","https://openalex.org/W2120635877","https://openalex.org/W2126372249","https://openalex.org/W2131054871","https://openalex.org/W2139730616","https://openalex.org/W2153215457","https://openalex.org/W2160428323","https://openalex.org/W4237131533"],"related_works":["https://openalex.org/W2086718556","https://openalex.org/W2167303720","https://openalex.org/W2012518269","https://openalex.org/W2046128376","https://openalex.org/W2363672756","https://openalex.org/W2109715593","https://openalex.org/W57688818","https://openalex.org/W1863436361","https://openalex.org/W1496086148","https://openalex.org/W1965891727"],"abstract_inverted_index":{"The":[0,57],"three-dimensional":[1],"(3D)":[2],"integration":[3],"enables":[4],"stacking":[5],"large":[6],"memory":[7,32],"on":[8,67],"top":[9],"of":[10,30,44,54,76,85,108],"chip-multi-processors":[11],"(CMPs).":[12],"Compared":[13],"to":[14,79,91],"the":[15,18,28,42,52,62,68,82,86,96,103,113,119],"2D":[16],"case,":[17],"extra":[19],"dimension":[20],"and":[21,94,121],"high":[22],"bandwidth":[23],"provide":[24],"more":[25],"options":[26],"for":[27],"design":[29,43,115],"on-chip":[31],"such":[33],"as":[34],"L2":[35,48],"caches.":[36],"In":[37,70],"this":[38],"work,":[39],"we":[40,72],"study":[41],"3D":[45,87,109],"stacked":[46],"set-associative":[47],"caches":[49],"through":[50],"managing":[51],"placement":[53,63,107],"cache":[55,88,110],"ways.":[56],"evaluation":[58],"results":[59,100],"show":[60,101],"that":[61,102],"has":[64],"an":[65],"impact":[66],"performance.":[69],"addition,":[71],"propose":[73],"a":[74],"technique":[75],"shadow":[77],"tag":[78],"dynamically":[80],"adjust":[81],"working":[83],"size":[84],"in":[89],"order":[90],"save":[92],"power":[93],"reduce":[95],"peak":[97],"temperature.":[98],"Evaluation":[99],"proposed":[104],"inter-layer":[105],"core-based-distribution":[106],"ways":[111],"is":[112],"best":[114],"option,":[116],"when":[117],"both":[118],"performance":[120],"thermal":[122],"management":[123],"are":[124],"considered.":[125]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}