{"id":"https://openalex.org/W2006331084","doi":"https://doi.org/10.1145/1577129.1577138","title":"Area-efficiency in CMP core design","display_name":"Area-efficiency in CMP core design","publication_year":2009,"publication_date":"2009-05-23","ids":{"openalex":"https://openalex.org/W2006331084","doi":"https://doi.org/10.1145/1577129.1577138","mag":"2006331084"},"language":"en","primary_location":{"id":"doi:10.1145/1577129.1577138","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1577129.1577138","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035434738","display_name":"Omid Azizi","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Omid Azizi","raw_affiliation_strings":["Stanford University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087686094","display_name":"Aqeel Mahesri","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aqeel Mahesri","raw_affiliation_strings":["University of Illinois at Urbana-Champaign","University of Illinois at Urbana Champaign"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Illinois at Urbana-Champaign","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"University of Illinois at Urbana Champaign","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104048759","display_name":"Sanjay J. Patel","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjay J. Patel","raw_affiliation_strings":["University of Illinois at Urbana-Champaign","University of Illinois at Urbana Champaign"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Illinois at Urbana-Champaign","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"University of Illinois at Urbana Champaign","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090469068","display_name":"Mark Horowitz","orcid":"https://orcid.org/0000-0003-3245-7542"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Horowitz","raw_affiliation_strings":["Stanford University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.0791388,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"37","issue":"2","first_page":"56","last_page":"65"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8057736158370972},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7141624093055725},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5943946838378906},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5750348567962646},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5663277506828308},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.49923181533813477},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.47753846645355225},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4741755723953247},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.43201589584350586},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.42359936237335205},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.42186790704727173},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4214155673980713},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39074939489364624},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3882385790348053},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.386192262172699},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3797664940357208},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08929494023323059}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8057736158370972},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7141624093055725},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5943946838378906},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5750348567962646},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5663277506828308},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.49923181533813477},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.47753846645355225},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4741755723953247},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.43201589584350586},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.42359936237335205},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.42186790704727173},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4214155673980713},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39074939489364624},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3882385790348053},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.386192262172699},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3797664940357208},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08929494023323059},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1577129.1577138","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1577129.1577138","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2016842024","https://openalex.org/W2036741467","https://openalex.org/W2041653803","https://openalex.org/W2048789167","https://openalex.org/W2063388447","https://openalex.org/W2099135670","https://openalex.org/W2099708455","https://openalex.org/W2109659793","https://openalex.org/W2111880608","https://openalex.org/W2120368896","https://openalex.org/W2121050483","https://openalex.org/W2145252892","https://openalex.org/W2145871983","https://openalex.org/W2154327203","https://openalex.org/W2157070686","https://openalex.org/W2169065640","https://openalex.org/W2170653240","https://openalex.org/W4244034697","https://openalex.org/W4248419771","https://openalex.org/W6681352259"],"related_works":["https://openalex.org/W4386869637","https://openalex.org/W2169880332","https://openalex.org/W3009555776","https://openalex.org/W4387251174","https://openalex.org/W2099305970","https://openalex.org/W4293143707","https://openalex.org/W2087838646","https://openalex.org/W2164091863","https://openalex.org/W2508455840","https://openalex.org/W2809170821"],"abstract_inverted_index":{"In":[0,58],"this":[1,116],"paper,":[2],"we":[3,61,89,104,114],"examine":[4],"the":[5,20,25,28,33,48,51,78,82,91,94,97,108,120],"area-performance":[6],"design":[7,22,30,54,73,172],"space":[8,23],"of":[9,27,46,55,81,153],"a":[10,14,39,56,70,111,124,155,165,175],"processing":[11],"core":[12,160],"for":[13,41,129,150],"chip":[15],"multiprocessor":[16],"(CMP),":[17],"considering":[18],"both":[19,47],"architectural":[21],"and":[24,50,64,96,164],"tradeoffs":[26,80,122],"physical":[29,52],"on":[31,134],"which":[32,103],"architecture":[34,95,128],"relies.":[35],"We":[36,75],"first":[37],"propose":[38],"methodology":[40,117],"performing":[42],"an":[43,100],"integrated":[44],"optimization":[45],"micro-architecture":[49],"circuit":[53,137],"microprocessor.":[57],"our":[59,140,151],"approach,":[60],"use":[62,105],"statistical":[63],"convex":[65],"fitting":[66],"methods":[67],"to":[68,106,118],"capture":[69],"large":[71],"micro-architectural":[72],"space.":[74],"then":[76],"characterize":[77],"area-delay":[79],"underlying":[83],"circuits":[84,98],"through":[85],"RTL":[86],"synthesis.":[87],"Finally,":[88],"establish":[90],"relationship":[92],"between":[93],"in":[99,123],"integrative":[101],"model,":[102],"optimize":[107],"processor.":[109],"As":[110],"case":[112],"study,":[113],"apply":[115],"explore":[119],"performance-area":[121],"highly":[125],"parallel":[126],"accelerator":[127],"visual":[130],"computing":[131],"applications.":[132],"Based":[133],"some":[135],"early":[136],"tradeoff":[138],"data,":[139],"results":[141],"indicate":[142],"that":[143],"two":[144],"separate":[145],"designs":[146],"are":[147],"performance/area":[148],"optimal":[149],"set":[152],"benchmarks:":[154],"simpler":[156],"single-issue,":[157],"2-way":[158],"multithreaded":[159,171],"running":[161,173],"at":[162,174],"high-frequency,":[163],"more":[166],"aggressively":[167],"tuned":[168],"dual-issue":[169],"4-way":[170],"lower":[176],"frequency.":[177]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
