{"id":"https://openalex.org/W1974120505","doi":"https://doi.org/10.1145/1555754.1555805","title":"A memory system design framework","display_name":"A memory system design framework","publication_year":2009,"publication_date":"2009-06-20","ids":{"openalex":"https://openalex.org/W1974120505","doi":"https://doi.org/10.1145/1555754.1555805","mag":"1974120505"},"language":"en","primary_location":{"id":"doi:10.1145/1555754.1555805","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1555754.1555805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th annual international symposium on Computer architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033963442","display_name":"Amin Firoozshahian","orcid":"https://orcid.org/0009-0009-0128-298X"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Amin Firoozshahian","raw_affiliation_strings":["Hicamp Systems Inc., Menlo Park, CA, USA"],"affiliations":[{"raw_affiliation_string":"Hicamp Systems Inc., Menlo Park, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000964076","display_name":"Alex Solomatnikov","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alex Solomatnikov","raw_affiliation_strings":["Hicamp Systems Inc., Menlo Park, CA, USA"],"affiliations":[{"raw_affiliation_string":"Hicamp Systems Inc., Menlo Park, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053715507","display_name":"Ofer Shacham","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ofer Shacham","raw_affiliation_strings":["Stanford University, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Stanford University, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019197913","display_name":"Zain Asgar","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zain Asgar","raw_affiliation_strings":["Stanford University, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Stanford University, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059607447","display_name":"Stephen Richardson","orcid":"https://orcid.org/0000-0003-4359-3638"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen Richardson","raw_affiliation_strings":["Stanford University, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Stanford University, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042148531","display_name":"Christos Kozyrakis","orcid":"https://orcid.org/0000-0002-3154-7530"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christos Kozyrakis","raw_affiliation_strings":["Stanford University, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Stanford University, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090469068","display_name":"Mark Horowitz","orcid":"https://orcid.org/0000-0003-3245-7542"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Horowitz","raw_affiliation_strings":["Stanford University, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Stanford University, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5033963442"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.9573,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.93951653,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"406","last_page":"417"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8306128978729248},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6469402313232422},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.6215828657150269},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5669300556182861},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5424414873123169},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5404707789421082},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.5386012196540833},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4937687814235687},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4871770739555359},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.4865075945854187},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4831404387950897},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4512438476085663},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4292256236076355},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4181232452392578},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.41569826006889343},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.38941138982772827},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.38745176792144775},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.3697332441806793},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3281714618206024},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2721121907234192},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2188158929347992}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8306128978729248},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6469402313232422},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.6215828657150269},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5669300556182861},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5424414873123169},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5404707789421082},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.5386012196540833},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4937687814235687},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4871770739555359},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4865075945854187},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4831404387950897},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4512438476085663},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4292256236076355},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4181232452392578},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.41569826006889343},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.38941138982772827},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.38745176792144775},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.3697332441806793},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3281714618206024},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2721121907234192},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2188158929347992},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1555754.1555805","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1555754.1555805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th annual international symposium on Computer architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W126742795","https://openalex.org/W199538813","https://openalex.org/W1575732703","https://openalex.org/W1850405760","https://openalex.org/W1986913310","https://openalex.org/W2004937484","https://openalex.org/W2022740893","https://openalex.org/W2029171059","https://openalex.org/W2034147186","https://openalex.org/W2037462607","https://openalex.org/W2097215759","https://openalex.org/W2113751407","https://openalex.org/W2113995939","https://openalex.org/W2144620832","https://openalex.org/W2146309320","https://openalex.org/W2148435977","https://openalex.org/W2148887883","https://openalex.org/W2149473197","https://openalex.org/W2149501383","https://openalex.org/W2152056423","https://openalex.org/W2152484003","https://openalex.org/W2156613948","https://openalex.org/W2157373341","https://openalex.org/W2160454978","https://openalex.org/W2166284215","https://openalex.org/W2171432528","https://openalex.org/W2171697422","https://openalex.org/W2465409697","https://openalex.org/W2955325419","https://openalex.org/W3113306529","https://openalex.org/W3142505176","https://openalex.org/W4253563417","https://openalex.org/W4312825855","https://openalex.org/W6681533205","https://openalex.org/W6681975522","https://openalex.org/W6696325823","https://openalex.org/W6719552900"],"related_works":["https://openalex.org/W2149371164","https://openalex.org/W2998091606","https://openalex.org/W2115955035","https://openalex.org/W2041174925","https://openalex.org/W1979830285","https://openalex.org/W2148966412","https://openalex.org/W4234107648","https://openalex.org/W4233816696","https://openalex.org/W2509861650","https://openalex.org/W2153372734"],"abstract_inverted_index":{"As":[0],"CPU":[1],"cores":[2],"become":[3],"building":[4],"blocks,":[5],"we":[6],"see":[7],"a":[8,55,91,123],"great":[9],"expansion":[10],"in":[11,66],"the":[12,23,43,68,98,107,119],"types":[13],"of":[14,45,77,102,112],"on-chip":[15],"memory":[16,31,72,93,108,125],"systems":[17,32,104],"proposed":[18],"for":[19,58,70],"CMPs.":[20],"Unfortunately,":[21],"designing":[22],"cache":[24,59],"and":[25,35,38,60,83,100,114],"protocol":[26,61],"controllers":[27],"to":[28,89],"support":[29],"these":[30],"is":[33],"complex,":[34],"their":[36],"concurrency":[37],"latency":[39],"characteristics":[40],"significantly":[41],"affect":[42],"performance":[44],"any":[46],"CMP.":[47],"To":[48],"address":[49],"this":[50,52],"problem,":[51],"paper":[53],"presents":[54],"microarchitecture":[56],"framework":[57,75,120],"controllers,":[62],"which":[63,86],"can":[64],"aid":[65],"generating":[67],"RTL":[69],"new":[71],"systems.":[73],"The":[74],"consists":[76],"three":[78],"pipelined":[79],"engines'":[80],"request-tracking,":[81],"state-manipulation,":[82],"data":[84,115],"movement'":[85],"are":[87],"programmed":[88],"implement":[90],"higher-level":[92],"model.":[94],"This":[95],"approach":[96],"simplifies":[97],"design":[99],"verification":[101],"CMP":[103],"by":[105],"decomposing":[106],"model":[109],"into":[110],"sequences":[111],"state":[113],"manipulations.":[116],"Moreover,":[117],"implementing":[118],"itself":[121],"produces":[122],"polymorphic":[124],"system.":[126]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}