{"id":"https://openalex.org/W2003312212","doi":"https://doi.org/10.1145/1555754.1555788","title":"Decoupled DIMM","display_name":"Decoupled DIMM","publication_year":2009,"publication_date":"2009-06-20","ids":{"openalex":"https://openalex.org/W2003312212","doi":"https://doi.org/10.1145/1555754.1555788","mag":"2003312212"},"language":"en","primary_location":{"id":"doi:10.1145/1555754.1555788","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1555754.1555788","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th annual international symposium on Computer architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046896624","display_name":"Hongzhong Zheng","orcid":"https://orcid.org/0000-0001-7696-9799"},"institutions":[{"id":"https://openalex.org/I39422238","display_name":"University of Illinois Chicago","ror":"https://ror.org/02mpq6x41","country_code":"US","type":"education","lineage":["https://openalex.org/I39422238"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hongzhong Zheng","raw_affiliation_strings":["University of Illinois at Chicago, Chicago, IL, USA"],"affiliations":[{"raw_affiliation_string":"University of Illinois at Chicago, Chicago, IL, USA","institution_ids":["https://openalex.org/I39422238"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073852078","display_name":"Lin Jiang","orcid":"https://orcid.org/0000-0003-3149-2733"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Lin","raw_affiliation_strings":["IBM Corp., Austin, TX, USA","IBM Corporation Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"IBM Corp., Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Corporation Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100423015","display_name":"Zhao Zhang","orcid":"https://orcid.org/0000-0002-2526-1712"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhao Zhang","raw_affiliation_strings":["Iowa State University, Ames, IA, USA","Iowa state university, Ames, IA, USA"],"affiliations":[{"raw_affiliation_string":"Iowa State University, Ames, IA, USA","institution_ids":["https://openalex.org/I173911158"]},{"raw_affiliation_string":"Iowa state university, Ames, IA, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101455512","display_name":"Zhichun Zhu","orcid":"https://orcid.org/0000-0002-7928-9024"},"institutions":[{"id":"https://openalex.org/I39422238","display_name":"University of Illinois Chicago","ror":"https://ror.org/02mpq6x41","country_code":"US","type":"education","lineage":["https://openalex.org/I39422238"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhichun Zhu","raw_affiliation_strings":["University of Illinois at Chicago, Chicago, IL, USA"],"affiliations":[{"raw_affiliation_string":"University of Illinois at Chicago, Chicago, IL, USA","institution_ids":["https://openalex.org/I39422238"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5046896624"],"corresponding_institution_ids":["https://openalex.org/I39422238"],"apc_list":null,"apc_paid":null,"fwci":5.8958,"has_fulltext":false,"cited_by_count":59,"citation_normalized_percentile":{"value":0.96526266,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"255","last_page":"266"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.8156294822692871},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.769753098487854},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.7393213510513306},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.6137982606887817},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5636001229286194},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5540763139724731},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5130361318588257},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.48174312710762024},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.4782477915287018},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.4765070974826813},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.46722280979156494},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.46064406633377075},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.4491528868675232},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4380885362625122},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4375409185886383},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.43218275904655457},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.42056870460510254},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.4059203267097473},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3588079810142517}],"concepts":[{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.8156294822692871},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.769753098487854},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.7393213510513306},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.6137982606887817},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5636001229286194},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5540763139724731},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5130361318588257},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.48174312710762024},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.4782477915287018},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4765070974826813},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.46722280979156494},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.46064406633377075},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.4491528868675232},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4380885362625122},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4375409185886383},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.43218275904655457},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.42056870460510254},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.4059203267097473},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3588079810142517}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1555754.1555788","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1555754.1555788","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th annual international symposium on Computer architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1488639170","https://openalex.org/W1973961119","https://openalex.org/W1987912519","https://openalex.org/W2044206819","https://openalex.org/W2085830671","https://openalex.org/W2096540124","https://openalex.org/W2098040113","https://openalex.org/W2100384468","https://openalex.org/W2100913437","https://openalex.org/W2101022290","https://openalex.org/W2102871765","https://openalex.org/W2106449576","https://openalex.org/W2115172404","https://openalex.org/W2120815613","https://openalex.org/W2122425314","https://openalex.org/W2122646225","https://openalex.org/W2123306627","https://openalex.org/W2129513794","https://openalex.org/W2129548165","https://openalex.org/W2145451976","https://openalex.org/W2149630066","https://openalex.org/W2153456949","https://openalex.org/W2156672769","https://openalex.org/W2162838417","https://openalex.org/W2165697076","https://openalex.org/W2167233984","https://openalex.org/W2171148960","https://openalex.org/W4236312724","https://openalex.org/W4236382111","https://openalex.org/W4285719527","https://openalex.org/W4288534138"],"related_works":["https://openalex.org/W2753615087","https://openalex.org/W2565280077","https://openalex.org/W4243576563","https://openalex.org/W4312264564","https://openalex.org/W4248614727","https://openalex.org/W2296275612","https://openalex.org/W1575240748","https://openalex.org/W2168550483","https://openalex.org/W2885040162","https://openalex.org/W2119473230"],"abstract_inverted_index":{"The":[0,106,137],"widespread":[1],"use":[2],"of":[3,68,139,144,154,163],"multicore":[4],"processors":[5],"has":[6],"dramatically":[7],"increased":[8],"the":[9,27,35,55,69,73,84,89,142],"demands":[10],"on":[11,103],"high":[12],"bandwidth":[13,112,145],"and":[14,30,88,93,128,150],"large":[15],"capacity":[16],"from":[17],"memory":[18,25,28,41,47,56,91,94,104,111,120,135,148,164],"systems.":[19],"In":[20,72],"a":[21,45,61,75,151],"conventional":[22],"DDR2/DDR3":[23],"DRAM":[24,31,70,86],"system,":[26],"bus":[29,57,149],"devices":[32,87],"run":[33],"at":[34,60],"same":[36],"data":[37,62,82],"rate.":[38],"To":[39],"improve":[40],"bandwidth,":[42],"we":[43],"propose":[44],"new":[46],"system":[48],"design":[49,107],"called":[50],"decoupled":[51],"DIMM":[52],"that":[53,67],"allows":[54],"to":[58,80,99,160],"operate":[59],"rate":[63],"much":[64],"higher":[65],"than":[66],"devices.":[71,136],"design,":[74],"synchronization":[76],"buffer":[77],"is":[78,97],"added":[79],"relay":[81],"between":[83,147],"slow":[85,134],"fast":[90],"bus;":[92],"access":[95,101],"scheduling":[96],"revised":[98],"avoid":[100],"conflicts":[102],"ranks.":[105],"not":[108],"only":[109],"improves":[110,124],"beyond":[113],"what":[114],"can":[115,156],"be":[116,158],"supported":[117],"by":[118,131],"current":[119],"devices,":[121,155],"but":[122],"also":[123,157],"reliability,":[125],"power":[126],"efficiency,":[127],"cost":[129],"effectiveness":[130],"using":[132],"relatively":[133],"idea":[138],"decoupling,":[140],"precisely":[141],"decoupling":[143],"match":[146],"single":[152],"rank":[153],"applied":[159],"other":[161],"types":[162],"systems":[165],"including":[166],"FB-DIMM.":[167]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":9},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":12},{"year":2012,"cited_by_count":10}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2016-06-24T00:00:00"}
