{"id":"https://openalex.org/W1989622980","doi":"https://doi.org/10.1145/1555754.1555770","title":"End-to-end register data-flow continuous self-test","display_name":"End-to-end register data-flow continuous self-test","publication_year":2009,"publication_date":"2009-06-20","ids":{"openalex":"https://openalex.org/W1989622980","doi":"https://doi.org/10.1145/1555754.1555770","mag":"1989622980"},"language":"en","primary_location":{"id":"doi:10.1145/1555754.1555770","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1555754.1555770","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th annual international symposium on Computer architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103578976","display_name":"Javier Carretero","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Javier Carretero","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111728780","display_name":"Pedro Chaparro","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Chaparro","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046613695","display_name":"Xavier Vera","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Xavier Vera","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020861175","display_name":"Jaume Abella","orcid":"https://orcid.org/0000-0001-7951-4028"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jaume Abella","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100733331","display_name":"Antonio Gonz\u00e1lez","orcid":"https://orcid.org/0000-0002-0009-0996"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Gonz\u00e1lez","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"[Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain]","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5103578976"],"corresponding_institution_ids":["https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":1.5829,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.83275777,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"105","last_page":"115"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6224133968353271},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5097655653953552},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.47319599986076355},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4687167704105377},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.444912850856781},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4415777623653412},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4337593913078308},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.42012718319892883},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3565232455730438},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3376513123512268},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3281248211860657},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3037416934967041},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25141197443008423},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22131448984146118},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1319408118724823},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12967854738235474}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6224133968353271},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5097655653953552},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.47319599986076355},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4687167704105377},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.444912850856781},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4415777623653412},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4337593913078308},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.42012718319892883},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3565232455730438},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3376513123512268},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3281248211860657},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3037416934967041},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25141197443008423},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22131448984146118},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1319408118724823},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12967854738235474},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1555754.1555770","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1555754.1555770","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th annual international symposium on Computer architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":44,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W147650083","https://openalex.org/W1559719544","https://openalex.org/W1864485850","https://openalex.org/W1959076962","https://openalex.org/W1981514768","https://openalex.org/W1985349959","https://openalex.org/W1998730330","https://openalex.org/W2004001391","https://openalex.org/W2008482633","https://openalex.org/W2020888328","https://openalex.org/W2025017266","https://openalex.org/W2034593585","https://openalex.org/W2088250010","https://openalex.org/W2102863623","https://openalex.org/W2114245820","https://openalex.org/W2114498748","https://openalex.org/W2114548296","https://openalex.org/W2116015411","https://openalex.org/W2116059696","https://openalex.org/W2117515905","https://openalex.org/W2118629573","https://openalex.org/W2121488803","https://openalex.org/W2122819799","https://openalex.org/W2128941141","https://openalex.org/W2128969704","https://openalex.org/W2129655902","https://openalex.org/W2129750565","https://openalex.org/W2138675194","https://openalex.org/W2143068308","https://openalex.org/W2146984159","https://openalex.org/W2149231606","https://openalex.org/W2151845324","https://openalex.org/W2155581886","https://openalex.org/W2160590289","https://openalex.org/W2166987606","https://openalex.org/W2169270029","https://openalex.org/W2250415240","https://openalex.org/W2468338882","https://openalex.org/W2543171663","https://openalex.org/W4230735214","https://openalex.org/W4243863555","https://openalex.org/W6602613798","https://openalex.org/W6605987033"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2056896932","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2041787842"],"abstract_inverted_index":{"While":[0],"Moore's":[1],"Law":[2],"predicts":[3],"the":[4,30,42,48],"ability":[5],"of":[6,33,44,90],"semi-conductor":[7],"industry":[8],"to":[9,40,54,67],"engineer":[10],"smaller":[11],"and":[12,16,71],"more":[13],"efficient":[14],"transistors":[15],"circuits,":[17],"there":[18,86],"are":[19],"serious":[20],"issues":[21],"not":[22],"contemplated":[23],"in":[24],"that":[25],"law.":[26],"One":[27],"concern":[28],"is":[29,87],"verification":[31],"effort":[32],"modern":[34],"computing":[35],"systems,":[36],"which":[37],"has":[38],"grown":[39],"dominate":[41],"cost":[43],"system":[45],"design.":[46],"On":[47],"other":[49],"hand,":[50],"technology":[51],"scaling":[52],"leads":[53],"burn-in":[55],"phase":[56],"out.":[57],"As":[58],"a":[59,88],"result,":[60],"in-the-field":[61],"error":[62],"rate":[63],"may":[64],"increase":[65],"due":[66],"both":[68],"actual":[69],"errors":[70],"latent":[72],"defects.":[73],"Whereas":[74],"data":[75],"can":[76],"be":[77],"protected":[78],"with":[79],"arithmetic":[80],"codes":[81],"(like":[82],"parity":[83],"or":[84],"ECC),":[85],"lack":[89],"cost-effective":[91],"mechanisms":[92],"for":[93],"control":[94],"logic.":[95]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
