{"id":"https://openalex.org/W2064977311","doi":"https://doi.org/10.1145/1555754.1555761","title":"Hybrid cache architecture with disparate memory technologies","display_name":"Hybrid cache architecture with disparate memory technologies","publication_year":2009,"publication_date":"2009-06-20","ids":{"openalex":"https://openalex.org/W2064977311","doi":"https://doi.org/10.1145/1555754.1555761","mag":"2064977311"},"language":"en","primary_location":{"id":"doi:10.1145/1555754.1555761","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1555754.1555761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th annual international symposium on Computer architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100837627","display_name":"Xiaoxia Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xiaoxia Wu","raw_affiliation_strings":["Pennsylvania State University, University Park, PA, USA"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108050345","display_name":"Jian Li","orcid":"https://orcid.org/0000-0002-5239-9469"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jian Li","raw_affiliation_strings":["IBM Austin Research Lab, Austin, TX, USA","IBM Austin Research Laboratories, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Lab, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratories, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008977627","display_name":"Lixin Zhang","orcid":"https://orcid.org/0000-0001-6799-3586"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lixin Zhang","raw_affiliation_strings":["IBM Austin Research Lab, Austin, TX, USA","IBM Austin Research Laboratories, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Lab, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratories, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073521684","display_name":"Evan W. Speight","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Evan Speight","raw_affiliation_strings":["IBM Austin Research Lab, Austin, TX, USA","IBM Austin Research Laboratories, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Lab, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratories, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113994263","display_name":"Ram Rajamony","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram Rajamony","raw_affiliation_strings":["IBM Austin Research Lab, Austin, TX, USA","IBM Austin Research Laboratories, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Lab, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratories, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100385336","display_name":"Yuan Xie","orcid":"https://orcid.org/0000-0003-2093-1788"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuan Xie","raw_affiliation_strings":["Pennsylvania State University, University Park, PA, USA"],"affiliations":[{"raw_affiliation_string":"Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100837627"],"corresponding_institution_ids":["https://openalex.org/I130769515"],"apc_list":null,"apc_paid":null,"fwci":24.655,"has_fulltext":false,"cited_by_count":334,"citation_normalized_percentile":{"value":0.99716044,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"34","last_page":"45"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8302950859069824},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7914301156997681},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.6459493637084961},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.6350155472755432},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.6084907054901123},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5816532969474792},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.5314760804176331},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5198591351509094},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5077093839645386},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4875745177268982},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4782116115093231},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.44404298067092896},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.423892080783844},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.4206107556819916},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38829293847084045},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24232172966003418}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8302950859069824},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7914301156997681},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.6459493637084961},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.6350155472755432},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6084907054901123},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5816532969474792},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.5314760804176331},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5198591351509094},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5077093839645386},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4875745177268982},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4782116115093231},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.44404298067092896},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.423892080783844},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.4206107556819916},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38829293847084045},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24232172966003418}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1555754.1555761","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1555754.1555761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th annual international symposium on Computer architecture","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.463.8280","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.463.8280","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://taco-hca.googlecode.com/svn/trunk/ISCA2009.pdf","raw_type":"text"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-133860","is_oa":false,"landing_page_url":"http://lbdiscover.ust.hk/uresolver?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=1063-6897&rft.volume=&rft.issue=&rft.date=2009&rft.spage=34&rft.aulast=Wu&rft.aufirst=Xiaoxia&rft.atitle=Hybrid+cache+architecture+with+disparate+memory+technologies&rft.title=Proceedings+-+International+Symposium+on+Computer+Architecture","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8600000143051147}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1978187377","https://openalex.org/W1982398126","https://openalex.org/W1987131925","https://openalex.org/W2005961863","https://openalex.org/W2023264348","https://openalex.org/W2035156756","https://openalex.org/W2047043979","https://openalex.org/W2064037464","https://openalex.org/W2084007230","https://openalex.org/W2112121929","https://openalex.org/W2113512876","https://openalex.org/W2117324528","https://openalex.org/W2119428232","https://openalex.org/W2122636510","https://openalex.org/W2126372249","https://openalex.org/W2131054871","https://openalex.org/W2131413854","https://openalex.org/W2132099976","https://openalex.org/W2133965199","https://openalex.org/W2139239342","https://openalex.org/W2143807959","https://openalex.org/W2148831941","https://openalex.org/W2153215457","https://openalex.org/W2156159026","https://openalex.org/W2157909358","https://openalex.org/W2160428323","https://openalex.org/W2169875292","https://openalex.org/W2181609752","https://openalex.org/W2543205889","https://openalex.org/W3139689176","https://openalex.org/W3169681048","https://openalex.org/W4206107614","https://openalex.org/W4237131533","https://openalex.org/W4323915530","https://openalex.org/W6631615826"],"related_works":["https://openalex.org/W2141363922","https://openalex.org/W2399041033","https://openalex.org/W2072955902","https://openalex.org/W2162744059","https://openalex.org/W2088347047","https://openalex.org/W3140186264","https://openalex.org/W12620440","https://openalex.org/W2000122388","https://openalex.org/W1576527819","https://openalex.org/W2397009038"],"abstract_inverted_index":{"Caching":[0],"techniques":[1],"have":[2,188],"been":[3,220],"an":[4,228],"efficient":[5],"mechanism":[6],"for":[7,203],"mitigating":[8],"the":[9,12,23,93,113,121,146,198,247,267,282,291],"effects":[10],"of":[11,25,95,112,123,135,155,173,182,192,200,254,276],"processor-memory":[13],"speed":[14],"gap.":[15],"Traditional":[16],"multi-level":[17],"SRAM-based":[18,89],"cache":[19,137,140,150,161,164,174,244,273],"hierarchies,":[20],"especially":[21],"in":[22,32,44,66,76,92,144,148,298],"context":[24],"chip":[26,284],"multiprocessors":[27],"(CMPs),":[28],"present":[29],"many":[30],"challenges":[31],"area":[33,249],"requirements,":[34],"core-to-cache":[35],"balance,":[36],"power":[37,82,102,208,299],"consumption,":[38],"and":[39,62,83,100,131,159,196,207],"design":[40,230,245,261,305],"complexity.":[41],"New":[42],"advancements":[43],"technology":[45,118,280],"enable":[46],"caches":[47],"to":[48,109,295],"be":[49,153,176],"built":[50],"from":[51],"other":[52],"technologies,":[53],"such":[54],"as":[55],"Embedded":[56],"DRAM":[57],"(EDRAM),":[58],"Magnetic":[59],"RAM":[60,64],"(MRAM),":[61],"Phase-change":[63],"(PRAM),":[65],"both":[67],"2D":[68],"chips":[69],"or":[70,163],"3D":[71,272],"stacked":[72],"chips.":[73],"Caches":[74],"fabricated":[75],"these":[77],"technologies":[78],"offer":[79],"dramatically":[80],"different":[81,184,193],"performance":[84],"characteristics":[85,115],"when":[86],"compared":[87],"with":[88],"caches,":[90],"particularly":[91],"areas":[94],"access":[96],"latency,":[97],"cell":[98],"density,":[99],"overall":[101],"consumption.":[103],"In":[104],"this":[105],"paper,":[106],"we":[107,225],"propose":[108],"take":[110],"advantage":[111],"best":[114],"that":[116,218,227],"each":[117,181],"offers,":[119],"through":[120],"use":[122],"Hybrid":[124],"Cache":[125],"Architecture":[126],"(HCA)":[127],"designs.":[128],"We":[129,187],"discuss":[130],"evaluate":[132],"two":[133],"types":[134],"hybrid":[136],"architectures:":[138],"inter":[139],"Level":[141],"HCA":[142,167,194,212],"(LHCA),":[143],"which":[145],"levels":[147],"a":[149,170,183,190,215,233,240,252,270,302],"hierarchy":[151],"can":[152,175,231],"made":[154],"disparate":[156],"memory":[157,185,279],"technologies;":[158],"intra":[160],"level":[162,172],"Region":[165],"based":[166],"(RHCA),":[168],"where":[169],"single":[171],"partitioned":[177],"into":[178],"multiple":[179],"regions,":[180],"technology.":[186],"studied":[189],"number":[191],"architectures":[195],"explored":[197],"potential":[199],"hardware":[201],"support":[202],"intra-cache":[204],"data":[205],"movement":[206],"consumption":[209,300],"management":[210],"within":[211,281],"caches.":[213],"Utilizing":[214],"full-system":[216],"simulator":[217],"has":[219],"validated":[221],"against":[222],"real":[223],"hardware,":[224],"demonstrate":[226],"LHCA":[229],"provide":[232],"geometric":[234],"mean":[235],"7%":[236],"IPC":[237,264,288],"improvement":[238,265,289],"over":[239,266,290,301],"baseline":[241,303],"3-level":[242],"SRAM":[243],"under":[246],"same":[248,283],"constraint":[250],"across":[251],"collection":[253],"25":[255],"workloads.":[256],"A":[257],"more":[258],"aggressive":[259],"RHCA-based":[260],"provides":[262],"12%":[263],"baseline.":[268,292],"Finally,":[269],"2-layer":[271],"stack":[274],"(3DHCA)":[275],"high":[277],"density":[278],"footprint":[285],"gives":[286],"18%":[287],"Furthermore,":[293],"up":[294],"70%":[296],"reduction":[297],"SRAM-only":[304],"is":[306],"achieved.":[307]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":16},{"year":2018,"cited_by_count":13},{"year":2017,"cited_by_count":28},{"year":2016,"cited_by_count":36},{"year":2015,"cited_by_count":35},{"year":2014,"cited_by_count":43},{"year":2013,"cited_by_count":49},{"year":2012,"cited_by_count":38}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
