{"id":"https://openalex.org/W1498896143","doi":"https://doi.org/10.1145/1543834.1543990","title":"Case study of finite resource optimization in FPGA using genetic algorithm","display_name":"Case study of finite resource optimization in FPGA using genetic algorithm","publication_year":2009,"publication_date":"2009-06-12","ids":{"openalex":"https://openalex.org/W1498896143","doi":"https://doi.org/10.1145/1543834.1543990","mag":"1498896143"},"language":"en","primary_location":{"id":"doi:10.1145/1543834.1543990","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1543834.1543990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=1064&context=electrical_facpubs","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101840276","display_name":"Jingxia Wang","orcid":"https://orcid.org/0000-0003-0627-2819"},"institutions":[{"id":"https://openalex.org/I182722699","display_name":"Shenzhen Polytechnic University","ror":"https://ror.org/00d2w9g53","country_code":"CN","type":"education","lineage":["https://openalex.org/I182722699"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"JingXia Wang","raw_affiliation_strings":["ShenZhen Polytechnic, ShenZhen, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ShenZhen Polytechnic, ShenZhen, China","institution_ids":["https://openalex.org/I182722699"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108061979","display_name":"Sin Ming Loo","orcid":"https://orcid.org/0000-0002-7395-0715"},"institutions":[{"id":"https://openalex.org/I120156002","display_name":"Boise State University","ror":"https://ror.org/02e3zdp86","country_code":"US","type":"education","lineage":["https://openalex.org/I120156002"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sin Ming Loo","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Boise, ID, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Boise, ID, USA","institution_ids":["https://openalex.org/I120156002"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0723,"has_fulltext":true,"cited_by_count":7,"citation_normalized_percentile":{"value":0.77195307,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"17","issue":null,"first_page":"989","last_page":"992"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9084267020225525},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7000802755355835},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.6263062953948975},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.5720874071121216},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.549902617931366},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5459659099578857},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.521148681640625},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.47328847646713257},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.469326913356781},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44985637068748474},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4486260712146759},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4117933213710785},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3910670578479767},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35874414443969727},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3276204466819763},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13495442271232605},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0840054452419281},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.0723421573638916}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9084267020225525},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7000802755355835},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.6263062953948975},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.5720874071121216},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.549902617931366},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5459659099578857},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.521148681640625},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.47328847646713257},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.469326913356781},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44985637068748474},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4486260712146759},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4117933213710785},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3910670578479767},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35874414443969727},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3276204466819763},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13495442271232605},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0840054452419281},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0723421573638916},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1543834.1543990","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1543834.1543990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation","raw_type":"proceedings-article"},{"id":"pmh:oai:scholarworks.boisestate.edu:electrical_facpubs-1064","is_oa":true,"landing_page_url":"https://scholarworks.boisestate.edu/electrical_facpubs/64","pdf_url":"https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=1064&context=electrical_facpubs","source":{"id":"https://openalex.org/S4377196366","display_name":"Scholar Works  (Boise State University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I120156002","host_organization_name":"Boise State University","host_organization_lineage":["https://openalex.org/I120156002"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical and Computer Engineering Faculty Publications and Presentations","raw_type":"text"},{"id":"mag:1498896143","is_oa":false,"landing_page_url":"https://dblp.uni-trier.de/db/journals/isca/isca17.html#WangL10","pdf_url":null,"source":{"id":"https://openalex.org/S67390379","display_name":"International journal of computers and their applications","issn_l":"1076-5204","issn":["1076-5204"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"International journal of computers and their applications","raw_type":null}],"best_oa_location":{"id":"pmh:oai:scholarworks.boisestate.edu:electrical_facpubs-1064","is_oa":true,"landing_page_url":"https://scholarworks.boisestate.edu/electrical_facpubs/64","pdf_url":"https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=1064&context=electrical_facpubs","source":{"id":"https://openalex.org/S4377196366","display_name":"Scholar Works  (Boise State University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I120156002","host_organization_name":"Boise State University","host_organization_lineage":["https://openalex.org/I120156002"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical and Computer Engineering Faculty Publications and Presentations","raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1498896143.pdf","grobid_xml":"https://content.openalex.org/works/W1498896143.grobid-xml"},"referenced_works_count":3,"referenced_works":["https://openalex.org/W1584298845","https://openalex.org/W1895654053","https://openalex.org/W2109633259"],"related_works":["https://openalex.org/W1972412824","https://openalex.org/W2558337280","https://openalex.org/W2895183628","https://openalex.org/W2766697190","https://openalex.org/W1801332854","https://openalex.org/W2003193909","https://openalex.org/W1997407353","https://openalex.org/W2111363079","https://openalex.org/W2283905284","https://openalex.org/W1606419106","https://openalex.org/W2145515907","https://openalex.org/W3152043746","https://openalex.org/W2025499700","https://openalex.org/W2088056559","https://openalex.org/W1971026932","https://openalex.org/W3191966537","https://openalex.org/W2904445802","https://openalex.org/W2139817798","https://openalex.org/W2106872678","https://openalex.org/W2122356583"],"abstract_inverted_index":{"Modern":[0],"Field-Programmable":[1],"Gate":[2],"Arrays":[3],"(FPGAs)":[4],"are":[5],"becoming":[6],"very":[7],"popular":[8],"in":[9,44,57,72],"embedded":[10],"systems":[11],"and":[12,32,35,49,64,90,109],"high-performance":[13],"applications.":[14],"FPGA":[15,46,58,83],"has":[16],"benefited":[17],"from":[18],"the":[19,39,86,104],"shrinking":[20],"of":[21,41],"transistor":[22],"feature":[23],"size,":[24],"which":[25],"allows":[26],"more":[27],"on-chip":[28],"reconfigurable":[29,42],"(e.g.":[30],"memories":[31],"look-up":[33],"tables)":[34],"routing":[36],"resources.":[37],"Unfortunately,":[38],"amount":[40],"resources":[43],"a":[45],"is":[47,70],"fixed":[48],"limited.":[50],"This":[51],"paper":[52],"investigates":[53],"an":[54],"application-mapping":[55],"scheme":[56],"by":[59],"utilizing":[60],"sequential":[61,79],"processing":[62],"units":[63],"task":[65],"specific":[66],"hardware.":[67],"Genetic":[68],"Algorithm":[69],"used":[71],"this":[73,96],"study.":[74],"We":[75],"found":[76],"that":[77],"placing":[78],"processor":[80],"cores":[81],"into":[82],"can":[84],"improve":[85],"resource":[87,107],"utilization":[88],"efficiency":[89],"achieved":[91],"acceptable":[92],"system":[93,110],"performance.":[94,111],"In":[95],"paper,":[97],"two":[98],"cases":[99],"were":[100],"studied":[101],"to":[102],"determine":[103],"trade-off":[105],"between":[106],"optimization":[108]},"counts_by_year":[{"year":2016,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}