{"id":"https://openalex.org/W2022202043","doi":"https://doi.org/10.1145/1534916.1534920","title":"Self-Measurement of Combinatorial Circuit Delays in FPGAs","display_name":"Self-Measurement of Combinatorial Circuit Delays in FPGAs","publication_year":2009,"publication_date":"2009-06-01","ids":{"openalex":"https://openalex.org/W2022202043","doi":"https://doi.org/10.1145/1534916.1534920","mag":"2022202043"},"language":"en","primary_location":{"id":"doi:10.1145/1534916.1534920","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1534916.1534920","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Justin S. J. Wong","raw_affiliation_strings":["Imperial College London","Imperial College London,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London,#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Imperial College London","Imperial College London,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London,#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Imperial College London","Imperial College London,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London,#TAB#","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5051758515"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":5.6282,"has_fulltext":false,"cited_by_count":61,"citation_normalized_percentile":{"value":0.96374823,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"2","issue":"2","first_page":"1","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8556116819381714},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7932323813438416},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6833394169807434},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.49873876571655273},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.49610885977745056},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.44150087237358093},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4233192801475525},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4028013348579407},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38090333342552185},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35462161898612976},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.19456589221954346},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.16644611954689026},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13654524087905884},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.10561051964759827},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09589681029319763},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07562315464019775}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8556116819381714},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7932323813438416},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6833394169807434},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.49873876571655273},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.49610885977745056},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.44150087237358093},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4233192801475525},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4028013348579407},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38090333342552185},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35462161898612976},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.19456589221954346},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.16644611954689026},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13654524087905884},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.10561051964759827},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09589681029319763},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07562315464019775},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1534916.1534920","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1534916.1534920","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G8360944955","display_name":null,"funder_award_id":"EP/C549481/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W142798423","https://openalex.org/W1532888190","https://openalex.org/W1572287951","https://openalex.org/W1984978262","https://openalex.org/W1991353737","https://openalex.org/W2016712281","https://openalex.org/W2031871682","https://openalex.org/W2055179355","https://openalex.org/W2096227207","https://openalex.org/W2099142412","https://openalex.org/W2102755988","https://openalex.org/W2121955149","https://openalex.org/W2126008551","https://openalex.org/W2126460975","https://openalex.org/W2127379989","https://openalex.org/W2141682861","https://openalex.org/W2144773387","https://openalex.org/W2154776455","https://openalex.org/W2155042027","https://openalex.org/W2170735577","https://openalex.org/W2178225970","https://openalex.org/W2532498749","https://openalex.org/W2607159714","https://openalex.org/W4235310052","https://openalex.org/W4255412321","https://openalex.org/W4302120964"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W1993041309","https://openalex.org/W4312888585","https://openalex.org/W2533938775"],"abstract_inverted_index":{"This":[0,150],"article":[1],"proposes":[2],"a":[3,35,61,109,165],"Built-In":[4],"Self-Test":[5],"(BIST)":[6],"method":[7,75,92,152],"to":[8,32,95,123,162],"accurately":[9],"measure":[10],"the":[11,21,43,51,65,74,79,83,125,134,138,154,169],"combinatorial":[12,44,55],"circuit":[13,45,56],"delays":[14,139],"on":[15,85,108,133],"an":[16,86],"FPGA.":[17],"The":[18,91],"flexibility":[19],"of":[20,37,53,64,67,73,78,81,106,120,140,167,171],"on-chip":[22],"clock":[23],"generation":[24],"capability":[25],"found":[26],"in":[27,42,114,160],"modern":[28],"FPGAs":[29,101,163],"is":[30,46],"employed":[31],"step":[33],"through":[34],"range":[36],"frequencies":[38],"until":[39],"timing":[40,62,158],"failure":[41],"detected.":[47],"In":[48],"this":[49],"way,":[50],"delay":[52,80],"any":[54],"can":[57],"be":[58],"determined":[59],"with":[60],"resolution":[63],"order":[66],"picoseconds.":[68],"Parallel":[69],"and":[70,99,137,143],"optimized":[71],"implementations":[72],"for":[76,156],"self-characterization":[77,105],"all":[82],"LUTs":[84,107],"FPGA":[87],"are":[88],"also":[89],"proposed.":[90],"was":[93,112],"applied":[94],"Altera":[96],"Cyclone":[97,110,135],"II":[98,111],"III":[100,136],".":[102],"A":[103],"complete":[104],"achieved":[113],"2.5":[115],"seconds,":[116],"utilizing":[117],"only":[118],"13kbit":[119],"block":[121],"RAM":[122],"store":[124],"results.":[126],"More":[127],"extensive":[128],"tests":[129],"were":[130,147],"carried":[131],"out":[132],"adder":[141],"circuits":[142],"embedded":[144],"multiplier":[145],"blocks":[146],"successfully":[148],"measured.":[149],"self-measurement":[151],"paves":[153],"way":[155],"matching":[157],"requirements":[159],"designs":[161],"as":[164],"means":[166],"combating":[168],"problem":[170],"process":[172],"variations.":[173]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":6}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}