{"id":"https://openalex.org/W2125596564","doi":"https://doi.org/10.1145/1531542.1531596","title":"Glitch-free design for multi-threshold CMOS NCL circuits","display_name":"Glitch-free design for multi-threshold CMOS NCL circuits","publication_year":2009,"publication_date":"2009-05-10","ids":{"openalex":"https://openalex.org/W2125596564","doi":"https://doi.org/10.1145/1531542.1531596","mag":"2125596564"},"language":"en","primary_location":{"id":"doi:10.1145/1531542.1531596","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1531542.1531596","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075250255","display_name":"Ahmad Al Zahrani","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ahmad Al Zahrani","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA","University of Arkansas, Fayetteville,, AR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"University of Arkansas, Fayetteville,, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025557826","display_name":"Andrew Bailey","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew Bailey","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA","University of Arkansas, Fayetteville,, AR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"University of Arkansas, Fayetteville,, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102064144","display_name":"Guoyuan Fu","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Guoyuan Fu","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA","University of Arkansas, Fayetteville,, AR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"University of Arkansas, Fayetteville,, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101644887","display_name":"Jia Di","orcid":"https://orcid.org/0000-0001-7718-0220"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jia Di","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA","University of Arkansas, Fayetteville,, AR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"University of Arkansas, Fayetteville,, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"215","last_page":"220"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.9028453826904297},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7318550944328308},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6190874576568604},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6145442128181458},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5675345063209534},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5278078317642212},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4973762333393097},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4675979018211365},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.44862040877342224},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.43783289194107056},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2612379491329193},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2506257891654968},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23401960730552673},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08703204989433289}],"concepts":[{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.9028453826904297},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7318550944328308},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6190874576568604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6145442128181458},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5675345063209534},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5278078317642212},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4973762333393097},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4675979018211365},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.44862040877342224},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.43783289194107056},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2612379491329193},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2506257891654968},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23401960730552673},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08703204989433289},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1531542.1531596","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1531542.1531596","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1601651202","https://openalex.org/W1882862660","https://openalex.org/W1976222993","https://openalex.org/W2039097694","https://openalex.org/W2088643059","https://openalex.org/W2103886509","https://openalex.org/W2114621701","https://openalex.org/W2144532166","https://openalex.org/W4236640259","https://openalex.org/W4241225399"],"related_works":["https://openalex.org/W2140328632","https://openalex.org/W2541225405","https://openalex.org/W2149184458","https://openalex.org/W4316660008","https://openalex.org/W2373956461","https://openalex.org/W1971856568","https://openalex.org/W1482101251","https://openalex.org/W2418067545","https://openalex.org/W2152324892","https://openalex.org/W2921949998"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3],"novel":[4],"design":[5,64,81],"is":[6,37,82],"proposed":[7,41,63,80],"for":[8],"eliminating":[9],"glitches":[10],"and":[11,43,55,85],"signal":[12],"bounces":[13],"during":[14],"wake-up":[15],"events":[16],"that":[17],"result":[18],"from":[19],"incorporating":[20],"multi-threshold":[21],"CMOS":[22],"(MTCMOS)":[23],"into":[24],"asynchronous":[25],"NULL":[26],"Convention":[27],"Logic":[28],"(NCL)":[29],"circuits.":[30],"A":[31],"one-stage":[32],"8x8":[33],"NCL":[34],"array":[35],"multiplier":[36],"designed":[38],"using":[39],"the":[40,46,62,70,79],"method":[42],"compared":[44],"with":[45],"previously":[47],"published":[48],"paradigm.":[49],"Evaluation":[50],"results":[51],"of":[52,61,74],"glitches,":[53],"throughput,":[54],"power":[56],"efficiency":[57],"have":[58],"shown":[59],"advantages":[60],"in":[65],"all":[66],"these":[67],"categories":[68],"over":[69],"state-of-the-art.":[71],"The":[72],"effect":[73],"supply":[75],"voltage":[76],"scaling":[77],"on":[78],"also":[83],"examined":[84],"presented.":[86]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}